Multi-phase-locked loop for data recovery

• US 6,442,225 B1
• Filed: 06/14/1999
• Issued: 08/27/2002
• Est. Priority Date: 06/14/1999
• Status: Expired

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Huang, Chen-chih
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Kim, Kevin
• Application Number:
  US09/332,066
• Time in Patent Office: 1,170 Days
• Field of Search: 375/376, 375/374, 327/156, 327/147, 327/153
• US Class Current: 375/376
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

The present invention provides a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide larger tolerance for data random jitter. It generates and output multiple sets of control signals (up_k/dn_k) via a multi-phase voltage controlled oscillator which generates a plurality of multi-phase clock signals for detecting the transition edge of data signal. Therefore, the phase error θ_e and the voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the control signals. A multi-phase-locked loop without dead zone thus can be provided.

Claims

1. A multi-phase-locked loop for data recovery comprising a phase detector, a charge pump, a loop filter and a voltage controlled oscillator, wherein:

said phase detector is constituted by N phase detection units (U₁, U₂, . . . , U_N, N is even, N≧

4);

said N phase detection units are connected in cascade configuration, and each phase detection unit contains a data signal input terminal for receiving a data signal from outside;

a clock signal input terminal for receiving the multi-phase clock signals (CK₁, CK₂, . . . , CK_N) from outside;

a delay signal input terminal for receiving a delay signal output from another phase detection unit;

a delay signal output terminal for outputting a delay signal; and

a charge/discharge control signal output terminal for outputting control signals for charge/discharge operations;

each of said N phase detection units generates a delay signal (D₁, D₂, . . . , D_N) according to an input data signal and the complement of a multi-phase clock signal;

the delay signal (D_j+1) generated by the (j+1)_th phase detection unit is input into the j_th phase detection unit via the j_th delay signal input terminal;

the delay signal (D₁) generated by the first phase detection unit is input into the N_th phase detection unit via the N_th delay signal input terminal;

the j_th phase detection unit (U_j′

1≦

j<

N, j is a positive integer) generates control signals (dn₁, dn₂, . . . , dn_N/2, up_N/2, . . . , up₂) for charge/discharge operations according to the delay signal (D_j) from the j_th phase detection unit, the delay signal (D_j+1) from the (j+1)_th phase detection unit, and the multi-phase clock signal (CK_j) which is applied to the j_th phase detection unit;

the N_th phase detection unit generates a charge control signal (up₁) according to the delay signal (D_n) from the N_th phase detection unit, the delay signal (D₁) from the first phase detection unit, and the multi-phase clock signal (CK_N) which is applied to the N_th phase detection unit;

said charge pump being constituted by N/2 charge and discharge units (CP₁, CP₂, . . . , CP_N/2), wherein the k_th (CP_k, 1≦

k≦

N/2) charge and discharge unit (CP_k) is employed to receive the k_th charge/discharge control signal set (up_k/dn_k) from said phase detector, and a current Ich_k is generated by the charge/discharge control signal set (up_k/dn_k);

the charge/discharge current Ich_k=(w_k×

up_k−

w_k×

dn_k)Iss, wherein w_k is a weighting value, Iss is a fixed current value, and w₁<

w₂<

. . . <

w_N/2;

the total charge/discharge current (Ich) from said charge pump equals to Ich₁+Ich₂+ . . . Ich_k+ . . . +Ich_N/2; and

said voltage controlled oscillator is a multi-phase voltage controlled oscillator, which outputs N multi-phase clock signals (CK₁, CK₂ . . . , CK_N), which are applied to said phase detectors, respectively.

2. The multi-phase-locked loop for data recovery as described in claim 1, wherein the phase difference between the multi-phase clock signal (CK_j+1) input to the (j+1)_th phase detection unit (U_j+1) and the multi-phase clock signal (CK_j) input to the j_t phase detection unit (U_j) equals to 2π

/N.

3. The multi-phase-locked loop for data recovery as described in claim 1, wherein each of said N phase detection unit comprises:

an inverter, a first flip-flop, an exclusive OR gate, and a second flip-flop;

said inverter inverting multi-phase clock signal which is to be input to each phase detection unit;

the first flip-flop generating a delay signal according to the complementary multi-phase clock signal from said inverter and the data signal;

the delay signal from said first flip-flop and the delay signal from the first flip-flop in another phase detection unit being input to the exclusive OR gate;

the second flip-flop generating a charge/discharge control signal according to the multi-phase clock signal and the output signal from said exclusive OR gate.

4. The multi-phase-locked loop for data recovery as described in claim 3, wherein said first flip-flop and said second flip-flop are D flip-flops.