Method for dynamic allocation and efficient sharing of functional unit datapaths

• US 6,442,672 B1
• Filed: 09/30/1998
• Issued: 08/27/2002
• Est. Priority Date: 09/30/1998
• Status: Expired due to Term

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Ganapathy, Kumar
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/163,741
• Time in Patent Office: 1,427 Days
• Field of Search: 712/1, 712/10, 712/16, 712/23, 712/28, 712/32, 712/35, 712/39, 712/43, 712/208, 712/221, 712/229, 712/3, 712/217, 712/228, 712/39.278, 712/211, 712/212, 712/209, 712/24, 712/210, 712/36, 712/205, 712/213, 712/206, 712/5, 712/6, 712/248, 712/245, 712/227, 712/181, 712/201, 375/240.25, 714/718, 714/733, 714/742, 714/743, 710/9, 710/129, 710/62, 710/104, 710/41, 710/131, 348/567, 348/584, 326/46
• US Class Current: 712/201
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30196 using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

The invention is a processing method and a processor architecture which contains multiple processors on the same silicon but which does not make a fixed compromise by statically assigning processing units to the processors but rather dynamically assigns such processing units so that they may be efficiently shared. The invention may provide the same functionality as was obtained with static allocation, and may be implemented on a single chip with much lower area for the same level of performance. The preferred architecture uses a mode bit that may be programatically set for passing control from a general purpose instruction decoder to a finite state machine. The preferred architecture further includes a multiplexer that uses the mode bit as its selection input.

Claims

1. A method of controlling data flow in a computer system, the method comprising:

selectively accessing, by an instruction decoder, at least one of a plurality of functional units of a processing unit;

selectively accessing, by a finite state machine, at least one of the plurality of functional units of the processing unit; and

dynamically assigning the instruction decoder and the finite state machine to access at least one of the plurality of functional units of the processing unit to control the flow of data in the computer system.

2. The method of claim 1 further comprising the instruction decoder controlling at least a portion of the data flow in the computer system and passing said control of the data flow in the computer system to the finite state machine according to instructions in the computer system.

3. The method of claim 1 wherein the at least one functional unit selectively accessed by the finite state machine is a specialized functional unit.

4. The method of claim 1 wherein the at least one functional unit selectively accessed by the instruction decoder is a general purpose execution unit.

5. The method of claim 1 further comprising the finite state machine controlling at least a portion of the data flow in the computer system and passing said control of the data flow in the computer system to the instruction decoder according to instructions in the computer system.

6. A processing architecture comprising:

a processing unit having at least one functional unit that takes data out of memory, operates on that data, and then puts the result back in memory disposed therein;

a first control mechanism that is configured to control flow of data in the at least one functional unit of the processing unit;

a second control mechanism that is configured to control flow of data in the at least one functional unit of the processing unit; and

a processor configured to dynamically assign either the first or second control mechanisms to at least one functional unit of the processing unit.

7. The processing architecture of claim 6 wherein the first control mechanism controls at least a portion of the data flow in the processing architecture and passes said control of the data flow in the processing architecture to the second control mechanism according to instructions in the processing architecture.

8. The processing architecture of claim 6 wherein the at least one functional unit of the processing unit is a specialized functional unit.

9. The processing architecture of claim 6 wherein the at least one functional unit of the processing unit is a general purpose execution unit.

10. The processing architecture of claim 6 wherein the first control mechanism comprises an instruction-decoder.

11. The processing architecture of claim 6 wherein the second control mechanism comprises a finite state machine.

12. The processing architecture of claim 6 wherein the second control mechanism controls at least a portion of the data flow in the processing architecture and passes said control of the data flow in the processing architecture to the first control mechanism according to instructions in the processing architecture.

13. A multiprocessor integrated chip comprising:

a processing unit having a plurality of functional units that take data out of memory, operate on that data, and then put the result back in memory;

a controller including an instruction decoder and a finite state machine, the controller issuing a plurality of control signals according to operations of the instruction decoder and/or the finite state machine; and

the controller configured to dynamically assign the control signals from the controller to the processing unit.

14. The multiprocessor integrated chip of claim 13 wherein the controller further comprises a multiplexor that enables the instruction decoder to pass control of the processing unit to the finite state machine.

15. The multiprocessor integrated chip of claim 13 wherein the finite state machine of the controller interoperates with one of the functional units of the processing unit, the one of the functional units comprising a specialized functional unit.

16. The multiprocessor integrated chip of claim 13 wherein the controller dynamically assigns the control signals to the processing unit according to a first input signal received from the instruction decoder and a second input signal received from the finite state machine.

17. The multiprocessor integrated chip of claim 16 further comprising a control register having a mode bit that may be set by an instruction executing in the instruction decoder and reset by the finite state machine.

18. The multiprocessor integrated chip of claim 13 wherein at least one of the plurality of functional units of the processing unit comprises a specialized functional unit.

19. The multiprocessor integrated chip of claim 13 wherein at least one of the plurality of functional units of the processing unit comprises a general purpose execution unit.