Method for dynamic allocation and efficient sharing of functional unit datapaths
First Claim
1. A method of controlling data flow in a computer system, the method comprising:
- selectively accessing, by an instruction decoder, at least one of a plurality of functional units of a processing unit;
selectively accessing, by a finite state machine, at least one of the plurality of functional units of the processing unit; and
dynamically assigning the instruction decoder and the finite state machine to access at least one of the plurality of functional units of the processing unit to control the flow of data in the computer system.
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Abstract
The invention is a processing method and a processor architecture which contains multiple processors on the same silicon but which does not make a fixed compromise by statically assigning processing units to the processors but rather dynamically assigns such processing units so that they may be efficiently shared. The invention may provide the same functionality as was obtained with static allocation, and may be implemented on a single chip with much lower area for the same level of performance. The preferred architecture uses a mode bit that may be programatically set for passing control from a general purpose instruction decoder to a finite state machine. The preferred architecture further includes a multiplexer that uses the mode bit as its selection input.
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Citations
19 Claims
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1. A method of controlling data flow in a computer system, the method comprising:
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selectively accessing, by an instruction decoder, at least one of a plurality of functional units of a processing unit;
selectively accessing, by a finite state machine, at least one of the plurality of functional units of the processing unit; and
dynamically assigning the instruction decoder and the finite state machine to access at least one of the plurality of functional units of the processing unit to control the flow of data in the computer system. - View Dependent Claims (2, 3, 4, 5)
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6. A processing architecture comprising:
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a processing unit having at least one functional unit that takes data out of memory, operates on that data, and then puts the result back in memory disposed therein;
a first control mechanism that is configured to control flow of data in the at least one functional unit of the processing unit;
a second control mechanism that is configured to control flow of data in the at least one functional unit of the processing unit; and
a processor configured to dynamically assign either the first or second control mechanisms to at least one functional unit of the processing unit. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A multiprocessor integrated chip comprising:
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a processing unit having a plurality of functional units that take data out of memory, operate on that data, and then put the result back in memory;
a controller including an instruction decoder and a finite state machine, the controller issuing a plurality of control signals according to operations of the instruction decoder and/or the finite state machine; and
the controller configured to dynamically assign the control signals from the controller to the processing unit. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification