Power saving by disabling memory block access for aligned NOP slots during fetch of multiple instruction words

• US 6,442,701 B1
• Filed: 10/08/1999
• Issued: 08/27/2002
• Est. Priority Date: 11/25/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hurd, Linda L.
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US09/415,526
• Time in Patent Office: 1,054 Days
• Field of Search: 713/320, 713/324, 712/24, 712/204, 717/141
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/30156 Special purpose encoding of instructions, e.g. Gray coding
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method of optimizing assembly code of a VLIW processor (10) or other processor that uses multiple-instruction words (20), each of which comprise instructions to be executed on different functional units (11d and 11e) of the processor (10). The instruction words (20) are modified, such that NOPs instructions are aligned in the same slot from one instruction to the next for a series of instructions. This modification permits memory access to be disabled so that those instructions are not fetched.

Claims

1. A method of reducing power usage by a processor that processes multiple-instruction words, said words having corresponding slots, one slot for each instruction in a word, said words being processed during one or more processor cycles, comprising the steps of:

comparing the syntax of a series of two or more of said words;

determining whether, from cycle to cycle, one or more NOP instructions can be moved to the same slot without substantially affecting functionality of said instruction words;

modifying at least one of said words in accordance with said determining step; and

disabling access to memory that stores instructions for said slot during fetch cycles for said series of instructions.

2. The method of claim 1, wherein said determining step determines whether a NOP instruction can be moved to another slot in the same word.

3. The method of claim 1, wherein said determining step determines whether a NOP instruction can be moved to another slot in a different word.

4. The method of claim 1, wherein said disabling step is accomplished by setting a control bit of said processor.

5. The method of claim 1, wherein said disabling step is accomplished by disabling memory strobing.

6. The method of claim 1, wherein said processor is a very long instruction word processor.

7. The method of claim 1, wherein said processor is a dual datapath processor.

8. The method of claim 1, wherein said multiple instruction words are fetch packets, such that all instructions in said instruction words are fetched from memory at substantially the same time.

9. The method of claim 1, wherein said processor executes multiple execute packets per fetch packet, such that one execute packet is executed per cycle.

10. The method of claim 1, wherein said processor executes a single execute packet per fetch packet, such that one fetch packet is executed per cycle.

11. A improved multiple-instruction word processor, said processor operable to execute words having corresponding slots, one slot for each instruction in the word, the improvement comprising:

a control bit operable to disable access to program memory associated with a slot of multiple-instruction words executed by said processor; and

means for clearing said control bit.

12. The processor of claim 11, wherein said control bit is set in response to a signal representing the beginning of a section of program code having a series of NOP instructions in the same slot.

13. The processor of claim 11, wherein said processor is a VLIW processor that executes multiple packets from the same fetch packet.

14. The processor of claim 11, wherein said processor is a VLIW processor that executes a single packet per fetch packet.

15. The processor of claim 11, wherein said processor is a dual-datapath processor.

16. The processor of claim 11, further comprising logic circuitry in communication with said control bit for disabling strobes to memory that stores instructions in said slot.