Memory module test system with reduced driver output impedance

• US 6,442,718 B1
• Filed: 08/23/1999
• Issued: 08/27/2002
• Est. Priority Date: 08/23/1999
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Tran, Dong, Krow-Lucal, Steven C., Jeffrey, David
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Torres, Joseph D.
• Application Number:
  US09/378,876
• Time in Patent Office: 1,100 Days
• Field of Search: 714/740, 714/742, 714/721, 365/200, 365/201
• US Class Current: 714/721
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A memory module test system with reduced driver output impedance. A test system includes a plurality of driver circuits, each of which is coupled to a transmission line on a loadboard. The loadboard includes a socket for insertion of the memory module to be tested. A test signal is generated and driven onto a transmission line by a driver circuit. A duplicate test signal is driven by a separate driver circuit onto a separate transmission line. The transmission lines carrying the test signal and duplicate test signal are electrically shorted on the loadboard. Electrically shorting these transmission lines effectively reduces their impedance by half. Multiple test signals generated by the test system are shorted in this manner in order to allow the electrical environment of the test system to more closely approximate that of the application environment of the tested memory module.

Claims

1. A test system for testing a memory module, said test system comprising:

a testing unit configured to generate a test output signal and a duplicate version of said test output signal to be used in a test operation of said memory module, said testing unit including a plurality of driver circuits, wherein said test output signal and said duplicate version of said test output signal are each driven by a separate driver circuit; and

a loadboard including a socket which accommodates insertion of said memory module, wherein said loadboard is configured to receive said test output signal and said duplicate version of said test output signal via respective transmission lines, and wherein said loadboard electrically shorts said respective transmission lines whereby an effective impedance associated with said transmission lines at their joining is reduced by approximately half the impedance of each of said separate driver circuits, and wherein said loadboard is a printed circuit board, the printed circuit board including a plurality of resistors and capacitors in order to electrically approximate the application environment of said memory module.

2. The test system as recited in claim 1, wherein said test unit is configured to generate at least a second test output signal and a duplicate version of said second output signal, wherein said second test output signal and said duplicate version of said second output signal are each driven by different driver circuits.

3. The test system as recited in claim 2, wherein said loadboard is configured to receive said second test output signal and said duplicate version of said second output test signal via a set of additional respective transmission lines, wherein said additional respective transmission lines are electrically shorted together on said loadboard.

4. The test system as recited in claim 1, wherein said driver circuits are configured to drive test signals to said memory module.

5. The test system as recited in claim 1, wherein said testing unit includes a plurality of instruments for measuring voltage and/or current.

6. The test system as recited in claim 1, wherein said memory module is adapted for insertion in a socket, said socket mounted upon said loadboard.

7. The test system as recited in claim 6, wherein said loadboard includes a plurality of jumper wires, each of said jumper wires configured to electrically short at least two of said transmission lines.

8. The test system as recited claim 7, wherein impedance of said transmission lines associated with each of said driver circuits is substantially 50 ohms.

9. The test system as recited in claim 1, wherein said memory module includes a plurality of Static Random Access Memory (SRAM) chips.

10. The testing unit as recited in claim 1, wherein said testing unit is configured to test said memory module for electrical characteristics and functionality.

11. A method for testing a memory module comprising:

generating a test output signal in a testing unit, said testing unit including a plurality of driver circuits, and a duplicate version of said test output signal to be used in a test operation of said memory module, wherein said test output signal and said duplicate version of said test output signal are each driven by a separate driver circuit; and

receiving said test output signal and said duplicate of said test output signal via respective transmission lines on a loadboard, said loadboard including a socket which accommodates insertion of said memory module, wherein said loadboard electrically shorts said respective transmission lines whereby an effective impedance associated with said transmission lines at their joining is reduced by approximately half the impedance of each of said separate driver circuits, wherein said loadboard is a printed circuit board, the printed circuit board including a plurality of resistors and capacitors in order to electrically approximate the application environment of said memory module.

12. The method as recited in claim 11, wherein said testing unit is configured to generate at least a second test output signal and a duplicate version of said second output signal, wherein said second test output signal and said duplicate version of said second output signal are each driven by different driver circuits.

13. The method as recited in claim 12, wherein said loadboard is configured to receive said second test output signals and said duplicate version of said second output test signal via a set of additional respective transmission lines, wherein said additional respective transmission lines are electrically shorted together on said loadboard.

14. The method as recited in claim 11, wherein said driver circuits are configured to drive test signals to said memory module.

15. The method as recited in claim 11, wherein said testing unit includes a plurality of instruments for measuring voltage and/or current.

16. The method as recited in claim 11, wherein said memory module is adapted for insertion in a socket, said socket mounted upon said loadboard.

17. The method as recited in claim 16, wherein said loadboard includes a plurality of jumper wires, each of said jumper wires configured to electrically short at least two of said transmission lines.

18. The method as recited in claim 17, wherein impedance of said transmission lines associated with each of said driver circuits is substantially 50 ohms.

19. The method as recited in claim 11, wherein said memory module includes a plurality of Static Random Access Memory (SRAM) chips.

20. The method as recited in claim 11, wherein said testing unit is configured to test said memory module for electrical characteristics and functionality.