Method and apparatus for testing circuits with multiple clocks

• US 6,442,722 B1
• Filed: 10/29/1999
• Issued: 08/27/2002
• Est. Priority Date: 10/29/1999
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Logicvision, Inc. (Siemens AG)
• Inventors: Buck, David P., Nadeau-Dostie, Benoit
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Torres, Joseph D.
• Application Number:
  US09/430,686
• Time in Patent Office: 1,033 Days
• Field of Search: 714/726, 714/729, 714/731
• US Class Current: 714/731
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/31858 Delay testing
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552

Abstract

A method of testing a circuit having two or more clock domains at respective domain test clock rates and under control of a main test clock signal, the circuit having core logic, a plurality of scannable memory elements, each having a clock input, an input connected to an output of the core logic and/or an output connected to an input to the core logic, and configurable in scan mode in which the memory elements are connected to define one or more scan chains in each domain and in normal mode in which the memory elements are connected to the core logic in normal operational mode, the method comprising configuring the memory elements in scan mode; concurrently clocking a test stimulus into each scan chain of each clock domain including, for each clock domain having a domain test clock signal which is synchronous with respect to the main test clock signal, clocking the test stimulus at a shift clock rate derived from the main test clock signal and, for each clock domain having a domain test clock signal which is asynchronous with respect to the main test clock signal, clocking all but a predetermined number of bits of the test stimulus at a first domain shift clock rate derived from the main test clock signal followed by clocking the predetermined number of bits of the test stimulus at a second domain shift clock rate corresponding to the domain test clock rate; configuring the memory elements of each scan chain in normal mode in which the memory elements of each scan chain are interconnected by the core logic in the normal operational mode; clocking each memory element in each scan chain at its respective domain test clock rate for at least one clock cycle thereof; configuring the memory elements in scan mode; and clocking a test response pattern out of each of the scan chains at its respective domain shift clock rate during a respective scan-out interval, all respective scan-out intervals overlapping in time for a plurality of clock cycles at the highest of the respective clock rates.

Claims

1. A method of testing a circuit having two or more clock domains at respective domain test clock rates and under control of a main test clock signal, said circuit having core logic, a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, said method comprising:

configuring said memory elements in scan mode;

concurrently clocking a test stimulus into each scan chain of each said clock domain including, for each clock domain having a domain test clock signal which is synchronous with respect to said main test clock signal, clocking said test stimulus at a shift clock rate derived from said main test clock signal and, for each clock domain having a domain test clock signal which is asynchronous with respect to said main test clock signal, clocking all but a predetermined number of bits of said test stimulus at a first domain shift clock rate derived from said main test clock signal followed by clocking said predetermined number of bits of said test stimulus at a second domain shift clock rate corresponding to said domain test clock rate;

configuring said memory elements of each scan chain in normal mode in which the memory elements of each scan chain are interconnected by said core logic in the normal operational mode;

clocking each memory element in each scan chain at its respective domain test clock rate for at least one clock cycle thereof;

configuring said memory elements in scan mode; and

clocking a test response pattern out of each of the scan chains at its respective domain shift clock rate during a respective scan-out interval, all respective scan-out intervals overlapping in time for a plurality of clock cycles at the highest of the respective clock rates.

2. A method, as defined in claim 1, for interacting synchronous and asynchronous domains, said configuring said memory elements of each scan chain in normal mode including configuring said memory elements of each scan chain of said interacting synchronous and asynchronous domains in normal mode during an overlapping normal mode interval in which the memory elements of each said scan chain of said interacting synchronous and asynchronous domains are interconnected by said core logic in the normal operational mode, all respective normal mode intervals overlapping in time such that a value captured by said memory elements is a combinational function of test data shifted into said memory elements.

3. A method as defined in claim 1, further including, for each signal path crossing a clock domain boundary between a pair of clock domains, suppressing capture in a memory element which is source or destination of a cross boundary signal if its associated destination or source memory element, respectively, in another domain is configured to perform a capture in said normal mode.

4. A method as defined in claim 3, for each clock domain having memory elements which are the source of multi-cycle signal paths, said predetermined number of bits being the number of cycles of said multi-cycle signal path, said step of concurrently clocking a test stimulus including storing all but the last one of said predetermined number of bits, and subsequently clocking stored bits at said second domain shift clock rate immediately prior to clocking in said last one of said bits.

5. A method as defined in claim 1, said step of clocking a test stimulus including, in each asynchronous domain, suppressing the clock signal applied to the clock input of said memory elements upon completing clocking of said all but a predetermined number of bits of said test stimulus;

and

re-activating said clock signal a predetermined number of clock cycles of said domain test clock signal prior to said normal mode cycle.

6. A method, as defined in claim 5, wherein the predetermined number of bits stored is one less than the number of cycles of said multi-cycle signal path.

7. A method as defined in claim 1, further including:

generating a domain configuration control signal for each said asynchronous clock domain;

activating said control signal at the beginning of each concurrently clocking operation; and

deactivating said control signal a predetermined number of clock cycles prior to launch of a test vector at each said memory element.

8. A method, as defined in claim 7, further including, for each asynchronous clock domain:

providing a domain test clock signal operable as a domain clock signal;

applying an active domain scan enable signal to a scan enable input of said memory elements in said domain when said control signal is active so as to configure said memory elements in scan mode;

detecting a transition of said domain control signal from active to inactive;

replacing said first domain shift clock signal with said second domain shift clock signal consequent to detecting said transition; and

applying an inactive domain scan enable signal to said scan enable input of said memory elements in said domain consequent to detecting said transition so as to configure said memory elements in normal mode.

9. A method as defined in claim 8, further including delaying detection of said transition for a predetermined delay period.

10. A method, as defined in claim 1, wherein the ratio of the clock rate of first and second domain shift clock rates is two or greater.

11. A method of testing a circuit having two or more clock domains at respective domain test clock rates and under control of a main test clock signal, said circuit having core logic, a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, said method comprising:

configuring said memory elements in scan mode including;

for each synchronous domain in which respective domain test clock signal is synchronous with respect to said main test clock signal, generating and applying active memory element configuration signals to memory elements in said synchronous domains;

for each asynchronous clock domain in which the domain test clock signal thereof is asynchronous with respect to said main test clock signal, generating an active configuration control signal, generating active memory element scan mode configuration signals and applying said memory element configuration signals to said memory elements; and

concurrently clocking a test stimulus into each scan chain of each said clock domain including;

for each synchronous clock domain, clocking said test stimulus at a domain shift clock rate derived from said main test clock signal and,

for each asynchronous clock domain;

generating respective first and second domain shift clock signals, said first domain shift clock signal being derived from said main test clock signal and said second domain shift clock signal being derived from said respective domain test clock signal;

selecting said first domain shift clock signal as a domain clock signal;

clocking all but a predetermined number of bits of said test stimulus under control of said domain clock signal;

generating an inactive configuration control signal,

suppressing said domain clock signal for a predetermined time interval in response to said inactive configuration control signal;

selecting said second domain shift clock signal as said domain clock signal;

activating said domain clock signal and clocking said predetermined number of bits of said test stimulus at under control of said domain clock signal;

configuring said memory elements of each scan chain in normal mode during an overlapping normal mode interval in which the memory elements of each scan chain are interconnected by said core logic in the normal operational mode, all respective normal mode intervals overlapping in time such that a value captured by said memory elements is a combinational function of test data shifted into said memory elements;

configuring said memory elements in scan mode including;

for each asynchronous clock domain, generating an active configuration control signal, generating active memory element scan mode configuration signals and applying said memory element configuration signals to said memory elements, and

for each synchronous domain, generating and applying active memory element configuration signals to memory elements in said synchronous domains;

clocking each memory element in each scan chain at its respective domain test clock rate for at least one clock cycle thereof;

clocking a test response pattern out of each of the scan chains including;

for each asynchronous clock domain, clocking said test response pattern under the control of said first domain shift clock signal; and

for each synchronous clock domain, clocking a test response pattern therefrom under control of its respective domain shift clock signal; and

analyzing said test response pattern from each said clock domain.

12. A method as defined in claim 11, wherein, in single-cycle scan paths, said predetermined number of bits is one and, in multi-cycle scan paths comprised of memory elements which source multi-cycle signal paths, said predetermined number of bits is a function of the number of cycles required by the longest multi-cycle path to propagate through said core logic.

13. A method as defined in claim 11, said step of configuring said memory elements in scan mode including generating a configuration control signal for each clock domain and responding to an active configuration control signal by applying an active scan enable signal to each memory element in said each clock domain and by selectively applying said domain shift clock signal to the clock input of said memory elements;

said concurrently clocking a test stimulus including shifting bits of said stimulus while said configuration control signal is active;

generating an inactive configuration control signal on the penultimate cycle of said clocking sequence in clock domains which do not include elements which source multi-cycle signal paths and generating an inactive configuration control signal on the third cycle prior to a capture cycle in clock domains which include elements which source multi-cycle signal paths;

continuously sampling said configuration control signal at the clock rate of said respective domain test clock signal for detecting a transition of said control signal from active to inactive;

suppressing the clock signal applied to the memory elements when said transition is detected until the cycle on which said test vector is launched from said memory elements;

said step of concurrently clocking a test response pattern out of said scan chains including;

generating an active configuration control signal;

responding to an active configuration control signal by generating and applying an active scan enable signal to the scan enable input of said memory elements and applying said respective shift clock signal to the clock input of said memory elements.

14. A test controller for use in testing an integrated circuit having core logic circuitry and two or more clock domains operable at respective domain clock rates, each clock domain having a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, said test controller comprising:

a primary test controller for controlling circuit test operations under control of a main test clock signal, said primary test controller being operable to;

concurrently load a test stimulus to each scan chain in each clock domain and receive response data from each said scan chain at respective domain shift clock rates;

generate respective domain shift clock signals derived from said main test clock signal for each clock domain;

generate a mode control signal for each synchronous clock domain; and

generate respective domain configuration control signal for each asynchronous clock domain in which the domain test clock signal is asynchronous with respect to said main test clock signal; and

an auxiliary test controller associated with each said asynchronous clock domain for controlling test operations therein under control of said primary test controller, each said auxiliary test controller being operable to generate a memory element clock signal derived from said respective domain shift clock signal when said respective domain configuration control signal is active and derived from said domain test clock signal when said domain configuration control signal is inactive;

each said auxiliary test controller being responsive to said respective configuration control signal by generating memory element configuration signals operable for configuring said memory elements in said scan mode or said normal mode.

15. A test controller as defined in claim 14, said primary test controller generating an active configuration control signal for each asynchronous clock domain at the beginning of a test stimulus loading sequence and a response data unloading sequence and generating an inactive configuration control signal a predetermined number of clock cycles of said respective domain shift clock signal prior to a capture cycle;

each said auxiliary test controller being responsive to an active configuration control signal by applying one or more local configuration signals to each memory element in its respective clock domain so as to configure said memory elements in scan mode and by applying said domain shift clock signal to the clock input of said memory elements;

each said auxiliary test controller being responsive to an inactive configuration control signal by suppressing the clock signal applied to said memory elements for a predetermined period of time, detecting the transition of said configuration control signal from active to inactive and, upon detecting said transition, applying a predetermined number of active edges of said respective domain test clock signal to the clock input of said memory elements and applying local configuration control signals to said memory elements prior to the last one of said predetermined number of active edges so as to configure said memory elements in normal mode to capture the response to said test vector and thereafter suppressing the clock signal applied to the clock input of said memory elements.

16. A test controller as defined in claim 15, said primary controller generating an inactive configuration control signal consequent to the penultimate edge of said domain shift clock signal of a loading sequence in single-cycle path clock domains.

17. A test controller as defined in claim 15, said primary controller generating an inactive configuration control signal consequent to a predetermined edge of said domain shift clock signal of a loading sequence in clock domains having memory elements which source multi-cycle signal paths, said predetermined edge being the number of cycles of said multi-cycle signal paths prior to the launch of a test vector bit.

18. A test controller, as defined in claim 17, wherein each auxiliary test controller which controls scan paths whose memory elements source multi-cycle signal paths further including storage means for storing test vector bits transmitted along the scan path while said clock signal is suppressed.

19. A test controller as defined in claim 14, each said auxiliary test controller including:

first means responsive to said configuration control signal and said domain test clock signal for generating memory element configuration signals for configuring said memory elements in a scan mode or normal mode;

second means responsive to said configuration control signal, said respective domain shift clock signal and said domain test clock signal for selectively applying one of said domain shift clock signal and said domain test clock signal to the clock input of its associated memory elements; and

third means for detecting the transition of said configuration control signal from active to inactive and responsive to a detected transition by selecting said domain test clock signal.

20. A test controller, as defined in claim 19, further including fourth means for delaying application of said configuration control signal to said third means for a predetermined period of time.

21. A test controller as defined in claim 19, said third means being operable to apply only a predetermined number of active clock edges of said domain test clock signal to said memory elements.

22. A test controller as defined in claim 19, said first means including retiming means clocked by said domain test clock signal for retiming said configuration control signal and outputting a local scan enable signal.

23. A test controller, as defined in claim 19, said first means including retiming means clocked by said domain test clock signal for retiming a clock enable signal from said primary controller and outputting a local clock enable signal.

24. A test controller as defined in claim 14, said auxiliary test controller including a clock signal generating circuit for generating and applying a local clock signal to the clock input of said memory elements, said clock signal generating signal including:

a shift clock generating circuit including;

an inverter receiving said configuration control signal and outputting an inverted configuration control signal;

a retiming element clocked by said domain shift clocked signal for retiming said inverted configuration control signal; and

an OR gate for receiving said inverted configuration control signal and said respective domain shift clock signal and producing a shift clock signal;

a capture clock signal generating circuit including;

a transition detector for detecting an active to inactive transition of said delayed configuration control signal and producing a capture clock disable signal;

a retiming element clocked by a source domain clock signal for producing a determined capture clock disable signal; and

an OR gate for receiving said retimed capture clock disable signal and said source domain clock signal for producing a capture clock signal;

an AND gate for receiving said shift clock signal and said capture clock signal and outputting said local clock signal.

25. A test controller, as defined in claim 24, said capture clock signal generating circuit further including a delay circuit clocked by said respective domain shift clock signal for receiving said configuration control signal and producing a delayed configuration control signal.

26. A test controller as defined in claim 24, said transition detector including timing means for defining the duration of said capture clock signal.

27. A test controller, as defined in claim 14, said auxiliary test controller being operable to control a clock domain having memory elements which source multi-cycle signal paths, including:

a memory element control signal generating circuit for generating and applying memory element configuration control signals to said memory elements;

a memory element clock signal generating circuit responsive to said configuration control signal, said domain shift control signal and a source domain clock signal for generating and applying a domain clock signal to the clock input of said memory elements; and

a scan path retiming circuit for retiming test stimulus output by said primary test controller and data captured in response to said test stimulus.

28. A test controller, as defined in claim 27, said primary test controller producing a clock enable signal under control of said domain shift clock signal, said memory element control signal generating circuit including:

a first retiming circuit clocked by domain clock signal for retiming said clock enable signal and outputting a retimed clock enable signal;

a second retiming circuit clocked by domain test clock signal for retiming said configuration control signal for outputting a scan mode control signal to said memory elements.

29. A test controller as defined in claim 27, said primary test controller producing a clock enable signal under control of said domain shift clock signal, said scan path retiming circuit including a test stimulus retiming circuit including:

storage means clocked by said domain shift clock signal for storing data bits from said test stimulus;

first selector means having an output connected to an input of said storage means and having a first input for receiving said test stimulus and a second input for receiving the output of said storage means and a data source select control signal for selectively applying one of said first and second inputs to the input of said storage means;

second selector means having an output connect to a scan chain in said domain and a first input for receiving said test stimulus data, a second input the output of said storage means and a third input for receiving a data source select control signal for selectively applying one of said second selector means inputs to said second selector means output; and

means responsive to said clock enable signal for generating said data source select control signal.

30. A test controller, as defined in claim 27, said scan path retiming circuit including a captured data retiming circuit for a scan path having memory elements which source single-cycle paths in a clock domain having a parallel multi-cycle signal path scan path, said retiming circuit including:

a selector means having a first input for receiving a scan output of a single cycle signal path scan path, a second input for receiving a signal of fixed value and a selector input for receiving said configuration control signal and operable to connect one of said inputs to the output of said selector means; and

a retiming element for retiming the output of said selector means under control of said domain shift clock signal.

31. A test controller for use in testing an integrated circuit having core logic circuitry and two or more clock domains operable at respective domain clock rates, each clock domain having a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, said test controller comprising:

a primary test controller for controlling circuit test operations under control of a main test clock signal, said primary test controller including;

a pseudo random pattern generator operable under control of said main test clock signal for concurrently generating a test stimulus for each scan chain in each clock domain;

a multiple input signature analyser operable under control of said main test clock signal for receiving and analysing response data from each said scan chain;

a circuit for generating a domain shift clock signal derived from said main test clock signal for each clock domain; and

a circuit for generating a configuration control signal for each said clock domain; and

an auxiliary test controller associated with each asynchronous clock domain for controlling test operations therein, each said auxiliary test controller receiving a respective domain shift clock signal from said primary controller and a respective domain test clock signal;

each said auxiliary test controller including;

means responsive to said configuration control signal for generating memory element configuration signals for configuring said memory elements in a scan mode or normal mode;

a clock signal generating circuit for generating and applying a local clock signal to the clock input of said memory elements, said clock signal generating circuit including;

a shift clock generating circuit responsive to said configuration control signal and said respective domain shift clock signal and producing a shift clock signal corresponding to said respective domain shift clock signal; and

a capture clock signal generating circuit responsive to said configuration control signal and said predetermined domain clock signal for producing a capture clock signal corresponding to said respective domain test clock signal; and

means receiving said shift clock signal and said capture clock and selectively outputting one of said shift and capture clock signals as said local clock signal.

32. A test controller as defined in claim 31, said shift clock generating circuit including:

an inverter receiving said configuration control signal and outputting an inverted configuration control signal;

a retiming element clocked by said domain shift clock signal for retiming said inverted configuration control signal; and

an OR gate for receiving said inverted configuration control signal and said domain shift clock signal and producing said shift clock.

33. A test controller, as defined in claim 32, said capture clock signal generating circuit including:

a delay circuit clocked by said domain shift clock signal for receiving said configuration control signal and producing a delayed configuration control signal;

a transition detector for detecting an active to inactive transition of said delayed configuration control signal and producing a capture clock disable signal;

a retiming element clocked by a source domain clock signal for producing a retimed capture clock disable signal; and

an OR gate for receiving said retimed capture clock disable signal and said source domain clock signal for producing a capture clock signal.

34. In a test controller for testing an integrated circuit having core logic circuitry and two or more clock domains operable at respective domain clock rates, each clock domain having a plurality of scannable memory elements, each having a clock input, an input connected to an output of said core logic and/or an output connected to an input to said core logic, and configurable in scan mode in which said memory elements are connected to define one or more scan chains in each said domain and in normal mode in which said memory elements are connected to said core logic in normal operational mode, the improvement comprising:

a primary controller for controlling circuit test operations under control of a main test clock signal and for controlling testing of synchronous clock domains whose domain test clock signal is synchronous with respect to said main test clock signal, said primary controller generating a respective shift clock signal derived from said main test clock signal for each clock domain, and a configuration control signal for each asynchronous clock domain in said circuit; and

an auxiliary controller associated with each asynchronous clock domain whose domain test clock signal is not synchronous with respect to said main test clock signal, and each said auxiliary controller being responsive to said primary controller for controlling testing of its associated clock domain, each auxiliary controller generating a memory element clock signal and responsive to an active configuration clock signal for applying its respective domain shift clock signal to said memory elements and responsive to an inactive configuration control signal for applying said domain test clock signal to said memory elements.