Method, circuit and apparatus for preserving and/or correcting product engineering information
First Claim
1. An integrated circuit, comprising:
- at least three non-volatile storage locations spaced from each other across at least a portion of the integrated circuit, wherein each of said storage locations is adapted to receive identical information; and
a circuit adapted to indicate correct information read from said storage locations when the identical information is read from a majority of said storage locations.
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0 Petitions
Accused Products
Abstract
A method, circuit and apparatus is provided for preserving and/or correcting product engineering information. Non-volatile storage devices reserved for receiving product engineering bits can either be contained in at least three separate storage locations spaced from each other across the integrated circuit or, alternatively, be contained in a single storage location area with error correction bits and/or words added to that location. In the first instance, redundant product engineering bits are written to each storage location. Product engineering bits read from a majority of those locations which have identical values are deemed valid. The addition of extra bits and/or words can be combined with the possibly defective product engineering bits to correct errors in those bits. Using redundancy to correct errors caused by charge loss or charge gain within previously stored product engineering values proves a beneficial outcome since testing the product engineering bit locations is not necessarily a viable solution. The product engineering bit locations may be programmed well before test patterns can be written to and read from those locations. Further, the uniquely programmed product engineering bits may unduly be lost during normal assembly of die into an integrated circuit package.
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Citations
15 Claims
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1. An integrated circuit, comprising:
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at least three non-volatile storage locations spaced from each other across at least a portion of the integrated circuit, wherein each of said storage locations is adapted to receive identical information; and
a circuit adapted to indicate correct information read from said storage locations when the identical information is read from a majority of said storage locations. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A storage location formed upon an integrated circuit, said storage location comprising:
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a first set of bit locations adapted to store information; and
a second set of bit locations adapted to determine corruption of said first set of bit locations, wherein at least the second set of bit locations is inaccessible during normal operation of the integrated circuit. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method, comprising:
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programming a first set of bit locations with information while programming a second set of bit locations with error correction bits, wherein at least the second set of bit locations is inaccessible during normal operation of an integrated circuit; and
reading the programmed information and the programmed error correction bits, wherein said error correction bits are adapted to detect and correct erroneous programmed information. - View Dependent Claims (14, 15)
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Specification