Preventing damaging of low voltage processor in high voltage system

• US 6,442,746 B1
• Filed: 12/21/1999
• Issued: 08/27/2002
• Est. Priority Date: 12/21/1999
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: James, Patrick D., Lam, Son H.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US09/471,618
• Time in Patent Office: 980 Days
• Field of Search: 713/300, 716/1, 716/2, 716/14-16
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A method and apparatus for protecting a low voltage processor inserted in a high voltage processor connector includes a circuit that determines whether power can be safely asserted to the connector, or whether power should be disabled due to a non-compliant processor. A method enables power to the connector upon a determination that a compliant processor, a termination card, or an empty connector is present.

Claims

1. A method for preventing damage to a low voltage processor inserted into a high voltage processor system, comprising:

determining whether a high voltage processor is present in the processor slot by logically combining a high voltage enable signal and a power enable signal from the processor;

determining whether a termination card is present in the processor slot;

determining whether the processor slot is empty; and

setting a power on okay signal on determining that a high voltage processor, a termination card, or an empty slot is present.

2. The method of claim 1, wherein the combining is performed in an exclusive NOR gate.

3. The method of claim 1, wherein determining whether the processor slot is empty comprises logically combining a high voltage enable signal and a power enable signal from the processor.

4. The method of claim 1, wherein determining whether a termination card is installed comprises logically combining a core identification bit 3 signal and a core voltage identification bit 4 signal complement from the processor, and a complement of a logical combination of a high voltage enable signal and a power enable signal from the processor.

5. The method of claim 4, wherein the logical combination of the core identification bit 3 and the core identification bit 4 complement is performed in an AND gate.

6. The method of claim 1, wherein the determinations are made in a different order.

7. A circuit, comprising:

a connector to receive an electrical component; and

connector logic operatively electrically connected to the connector for logically combining signals from the component to determine the identity of the component, the connector logic comprising

an exclusive or gate having two inputs connectable to a high voltage enable signal and a power enable signal;

an inverter connected to the output of the exclusive or gate;

a second inverter with an input connectable to a core identification bit 4 signal slot;

an and gate having three inputs, the first input connected to the output of the inverter, the second input connected to the output of the second inverter, and the third input connectable to a core identification bit 3 signal slot; and

an or gate having two inputs, the first input connected to the output of the exclusive or gate, and the second input connected to the output of the and gate.

8. The circuit of claim 7, wherein the connector logic is configured to assert a signal to power to the connector upon a determination that power may safely be asserted to the connector.

9. The circuit of claim 7, wherein the connector logic is configured to determine whether the connector is empty, or whether the connector contains a high voltage compliant processor, a termination card or a non-high voltage processor.

10. A method comprising:

determining whether power to a processor connector may be safely asserted, including determining whether a high-voltage processor is installed by logically combining a high voltage enable signal and a power enable signal; and

asserting power to the processor connector on a determination that power may be safely asserted.

11. A method comprising:

determining whether power to a processor connector may be safely asserted, including determining whether the processor connector is empty by logically combining a high voltage enable signal and a power enable signal; and

asserting power to the processor connector on a determination that power may be safely asserted.

12. A method comprising:

determining whether power to a processor connector may be safely asserted, including determining whether a termination card is installed in the processor connector by logically combining a core identification bit 3 signal, a core identification bit 4 complement, and a complement of a logical combination of a high voltage enable signal and a power enable signal; and

asserting power to the processor connector on a determination that power may be safely asserted.

13. A connector for a processor, comprising:

a plurality of processor contacts configured to accept a connector component;

a circuit for enabling power to the connector upon a determination that the component is high voltage compliant, wherein the circuit comprises connector logic for logically combining signals from the component installed in the connector to determine the identity of the component, the connector logic including;

first logic for combining a high voltage enable signal and a power enable signal;

second logic for inverting the output of the first logic;

third logic for inverting a core identification bit 4 signal;

fourth logic for combining the output of the second logic, the output of the second logic, and a core identification bit 3 signal; and

fifth logic for combining the output of the first logic and the output of the fourth logic.

14. The connector of claim 13, wherein the first logic is an exclusive NOR gate.

15. The connector of claim 13, wherein the fourth logic is an AND gate.

16. The connector of claim 13, wherein the fifth logic is an OR gate.

17. A motherboard, comprising:

a processor connector;

a power supply operatively electrically connected to the motherboard and the processor connector; and

a circuit for enabling power to the connector upon a determination that a termination card or a high voltage compliant processor is installed in the connector slot, the circuit including;

connector logic for logically combining signals from the component installed in the connector to determine the identity of the component, the connector logic including;

first logic for combining a high voltage enable signal and a power enable signal;

second logic for inverting the output of the first logic;

third logic for inverting a core identification bit 4 signal;

fourth logic for combining the output of the second logic, the output of the second logic, and a core identification bit 3 signal; and

fifth logic for combining the output of the first logic and the output of the fourth logic.

18. The motherboard of claim 17, wherein the circuit is contained within the processor connector.