Selective oxide deposition in the bottom of a trench

• US 6,444,528 B1
• Filed: 08/16/2000
• Issued: 09/03/2002
• Est. Priority Date: 08/16/2000
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Murphy, James J.
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/640,496
• Time in Patent Office: 748 Days
• Field of Search: 438/138, 438/268, 438/270, 438/424, 438/430, 438/589, 438/981
• US Class Current: 438/270
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness. The thicker dielectric layer at the bottom substantially reduces gate charge to reduce the Miller Capacitance effect, thereby increasing the efficiency of the semiconductor device and prolonging its life.

Claims

1. A method of forming a gate dielectric layer of a trench field effect transistor, the method comprising the steps of:

forming a trench in a silicon substrate;

growing a thermal oxide layer on the sidewalls and bottom of the trench;

etching away the thermal oxide layer from the bottom of the trench to expose the silicon substrate;

depositing a selective oxide layer at the bottom of the trench over the silicon substrate to a desired thickness, wherein the desired thickness is greater than a thickness of the thermal oxide layer on the sidewalls of the trench;

removing the thermal oxide layer from the sidewalls of the trench; and

forming a gate oxide layer on the sidewalls of the trench, to a thickness that is less than the desired thickness of the selective oxide layer.

2. The method of claim 1, wherein the selective oxide layer is deposited according to a deposition process wherein oxide is primarily directed for deposition on the exposed silicon substrate surface.

3. The method of claim 1, wherein the thermal oxide layer is grown according to a local oxidation of silicon (LOCOS) process.

4. The method of claim of claim 1, wherein the desired thickness is approximately between 4000 Å

and 5000 Å

.

5. The method of claim 1, wherein the step of forming a trench further comprises the steps of:

depositing a thin oxide layer on a top surface of the silicon substrate;

depositing a patterned nitride film over the thin oxide layer;

applying a photoresist layer over the patterned nitride film;

etching the nitride film according to a pattern in the patterned nitride film; and

removing the photoresist layer.

6. A method of forming a gate dielectric layer for a trench semiconductor device, the method comprising the steps of:

forming a first trench in a silicon substrate;

growing a thermal oxide layer on the sidewalls and bottom of the first trench;

depositing a layer of nitride over the thermal oxide layer;

etching away the thermal oxide layer and the nitride layer from the bottom of the first trench;

forming a second trench at the bottom of the first trench to expose the silicon substrate on the sidewalls and bottom of the second trench; and

depositing a selective oxide layer into the second trench over the silicon substrate to a desired thickness, wherein the desired thickness corresponds to a depth of the second trench and is greater than a thickness of the thermal oxide layer on the sidewalls of the trench.

7. The method of claim 6 further comprising the step of selectively removing portions of the nitride layer from the silicon substrate.

8. The method of claim 6 further comprising the step of densifying the selective oxide layer to a density approximately equal to the thermal oxide layer on the sidewalls of the trench.

9. The method of claim 6, wherein the second trench is formed to a depth of approximately 4000 Å

below the bottom of the first trench.

10. The method of claim 6 further comprising the step of annealing the semiconductor device to densify the selective oxide layer.

11. A method of manufacturing a trench MOSFET, comprising the steps of:

forming a plurality of trenches in a semiconductor substrate having a first conductivity type, each trench defined by sidewalls and a bottom;

growing a thermal oxide on the sidewalls and the bottom of the trenches;

etching away the thermal oxide layer on the sidewalls and the bottom of the trenches to expose portions of a surface of the semiconductor substrate;

depositing a selective oxide layer on the bottom of the trenches over the exposed portions of the surface of the semiconductor substrate to a predetermined thickness, wherein the predetermined thickness is greater than a thickness of the thermal oxide layer on the sidewalls of the trenches;

lining the oxide layer and selective oxide layer and filling the trenches with polysilicon;

doping the polysilicon with a dopant having a first conductivity type;

patterning the substrate and implanting a dopant having a second conductivity type to form a well into which the trenches are positioned;

patterning the substrate and implanting a dopant having the second conductivity type to form a plurality of heavy bodies positioned within the well and between trenches; and

patterning the substrate and implanting a dopant having the first conductivity type to form source regions within the well, the source regions positioned adjacent to and on opposite sides of each trench.

12. A method of forming a trench MOSFET comprising the steps of:

forming a plurality of primary trenches in a semiconductor substrate, each primary trench having sidewalls and a bottom;

forming a first dielectric layer on the sidewalls and the bottom of the primary trenches;

forming a second dielectric layer over the first dielectric layer;

etching through the first and second dielectric layers at the bottom of the primary trenches and into the semiconductor substrate to form a plurality of secondary trenches;

filling the secondary trenches with an oxide to a predetermined depth;

removing the first and second dielectric layers from the primary trench sidewalls; and

forming a gate oxide layer on the primary trench sidewalls.

13. The method of claim 12 wherein the step of etching is performed using an isotropic etch.

14. The method of claim 12 wherein the step of etching comprises the steps of:

performing an isotropic etch; and

performing an anisotropic etch,

wherein the isotropic etch is controlled so that the secondary trenches can be made as wide or wider than the primary trenches.

15. The method of claim 12 wherein the first dielectric layer is an oxide.

16. The method of claim 12 wherein the second dielectric is a nitride.

17. The method of claim 12 wherein the thickness of the oxide layer in the secondary trenches is greater than the thickness of the gate oxide.

18. The method of claim 12 wherein the secondary trenches are formed to a depth of approximately 4000 Å

.

19. The method of claim 12 further comprising the steps of:

forming a thin oxide layer over a top surface of the silicon substrate prior to the step of forming the primary trenches;

forming a nitride layer over the thin oxide layer;

patterning the nitride layer; and

etching through the thin oxide and nitride layers according to the patterned nitride layer.

20. The method of claim 12 further comprising the steps of:

forming a hardmask over a top surface of the silicon substrate prior to the step of forming the primary trenches;

patterning the hardmask; and

etching through the hardmask according to the patterned hardmask.

21. The method of claim 20 further comprising the step of removing the hardmask using chemical mechanical polishing.