Interfacial oxidation process for high-k gate dielectric process integration

• US 6,444,592 B1
• Filed: 06/20/2000
• Issued: 09/03/2002
• Est. Priority Date: 06/20/2000
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Newbury, Joseph S., McFeely, Fenton Read, Cartier, Eduard A., Copel, Matthew W., Chan, Kevin K., Buchanan, Douglas A., Gousev, Evgeni P., Ballantine, Arne W., Varekamp, Patrick R., Zabel, Theodore H., Okorn-Schmidt, Harald F., DʼEmic, Christopher P.
• Primary Examiner(s): Sherry, Michael
• Assistant Examiner(s): KILDAY, LISA A
• Application Number:
  US09/597,765
• Time in Patent Office: 805 Days
• Field of Search: 438/758, 438/769, 438/770, 438/775, 438/785, 257/410
• US Class Current: 438/770
• CPC Class Codes: H01L 21/02145 the material containing aluminium, e.g. AlSiOx
• CPC Class Codes: H01L 21/02197 the material having a perovskite structure, e.g. BaTiO3
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02247 formation by nitridation, e.g. nitridation of the substrate
• CPC Class Codes: H01L 21/02249 formation by combined oxidation and nitridation performed simultaneously
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Abstract

A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 Å; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.

Claims

1. A method for fabricating a semiconductor device including a high-k dielectric material therein comprising the steps of:

(a) forming an interfacial layer on a device region of a semiconductor substrate, said interfacial layer comprising an oxynitride, nitride or mixtures and multilayers thereof and having a thickness of less than 10 Å

; and

(b) forming a high-k dielectric layer on said interfacial layer, said high-k dielectric having a dielectric constant, k, of greater than 8.

2. The method of claim 1 wherein said interfacial layer is formed by a rapid thermal oxynitridation (RTON) process, a rapid thermal nitridation (RTN) process or combinations thereof.

3. The method of claim 2 wherein said RTON or RTN process is carried out in an ambient including NO, N₂O or combinations thereof.

4. The method of claim 3 wherein said ambient is used in conjunction with an inert carrier gas.

5. The method of claim 2 wherein said RTON or RTN process is carried out at atmospheric or a reduced pressure below atmospheric.

6. The method of claim 2 wherein said RTON or RTN process is carried out at a temperature of about 400°

C. or above for a time period of from about 180 seconds or less.

7. The method of claim 6 wherein said RTON or RTN process is carried out at a temperature of from about 700°

to about 900°

C. for a time period of from about 5 to about 60 seconds.

8. The method of claim 2 further comprising a remote or direct plasma nitridation or oxynitridation process.

9. The method of claim 8 wherein said nitridation process includes exposure to a nitrogen-containing plasma for about 5 to about 300 seconds.

10. The method of claim 8 further comprising an nitrogen implantation process, said nitrogen implantation being carried out at an energy of 10 keV or below.

11. The method of claim 2 further comprising a nitrogen implantation process, said nitrogen implantation being carried out at an energy of 10 keV or below.

12. The method of claim 1 wherein said high-k dielectric layer is a binary oxide, a silicate or aluminate of a binary oxide, a perovskite-type oxide or any combination or multilayer thereof.

13. The method of claim 12 wherein said perovskite type oxide includes a titanate system material, a niobate system material, a tantalate system material, a tungsten-bronze system or a Bi-layered perovskite system material.

14. The method of claim 1, wherein said interfacial layer further comprises an oxide.

15. The method of claim 14 wherein said oxide is formed by a remote or direct plasma oxidation process.

16. The method of claim 15 wherein said plasma oxidation process includes O₂ plasma immersion of Si wafers for about 5 to about 300 seconds.

17. The method of claim 14 wherein said oxide is formed by an ozone process.

18. The method of claim 14 wherein said oxide is formed by a low-energy oxygen implantation process and a rapid thermal anneal process.

19. The method of claim 18 wherein said low-energy oxygen implantation process is carried out using an energy of 5 keV or below.

20. The method of claim 18 wherein said rapid thermal anneal is carried out at a temperature of from about 700°

to about 1100°

C. for a time period of from about 5 to about 60 seconds.

21. The method of claim 14, wherein said oxide is formed by a rapid thermal oxidation (RTO) process.

22. The method of claim 1 wherein step (a) is carried out in a chamber that is capable of rotating said substrate.