Semiconductor device having trench-structured rectangular unit cells

• US 6,445,036 B1
• Filed: 08/23/2000
• Issued: 09/03/2002
• Est. Priority Date: 08/23/1999
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Maruoka, Michiaki
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Nadav, Ori
• Application Number:
  US09/643,764
• Time in Patent Office: 741 Days
• Field of Search: 257/327-334, 257/401, 438/268-274
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device is provided which has a structure being suitable for scale-down of cells and is capable of, without an increase in channel resistance, improving a resistance property against device breakdown required when a semiconductor device breaks down due to inverse voltages applied. In the above semiconductor device, a source region narrowing section, in which width dimension on a plane of a source region is partially limited, is formed at the cell corner section disposed on diagonal lines and in a vicinity of the diagonal lines.

Claims

1. A semiconductor device having a plurality of trench-structured rectangular unit cells comprising:

a first conductive type drain region;

a second conductive type base region formed adjacent to said first conductive type drain region;

a trench formed in an area surrounding said second conductive type base region;

a gate electrode formed within said trench with a gate insulating film interposed between said gate electrode and said trench;

a first conductive type source region having a continuous shape formed along said trench on the surface of said second conductive type base region; and

a region having no source is formed at a center of a rectangular surface of each of said trench-structured rectangular unit cells and extends outwardly on diagonal lines that radially extend from said center towards corners of each of said trench-structured rectangular unit cells.

2. A semiconductor device having a plurality of trench-structured rectangular unit cells comprising:

a first conductive type drain region;

a second conductive type base region formed adjacent to said first conductive type drain region;

a trench formed in an area surrounding said second conductive type base region;

a gate electrode formed within said trench with a gate insulating film interposed between said gate electrode and said trench;

a first conductive type source region having a continuous shape formed along said trench on the surface of said second conductive type base region; and

a source region narrowing section which partially limits width dimensions on a plane of said first conductive type source region is formed on diagonal lines on a rectangular surface of said trench-structured rectangular unit cells and in a vicinity of said diagonal lines of said trench-structured rectangular unit cells, wherein said diagonal lines extend from corners of said rectangular surface towards a center of said rectangular surface, and said source region narrowing section has a width which is less than a width of other sections of said first conductive type source region.

3. The semiconductor device according to claim 2, wherein each of said trench-structured rectangular unit cells is coated with an interlayer dielectric in which a source and base contact aperture section is formed and a source electrode is formed through said source and base contact aperture section.

4. The semiconductor device according to claim 3, wherein said source region narrowing section is so structured that said first conductive type source region is narrowed by an arbitrary dimension on said diagonal lines of each of said first conductive type unit cells in a direction from said source and base contact aperture section in said interlayer dielectric toward a corner section of each of said trench-structured rectangular unit cells.

5. The semiconductor device according to claim 2, wherein said source region narrowing section is formed at a time of formation of said first conductive type source region after a second conductive semiconductor region containing an impurity concentration being higher than that of said second conductive type base region is formed in advance at a part of a place where said first conductive type source region is to be formed.