Circuit technique for improved current matching in charge pump PLLS

• US 6,445,211 B1
• Filed: 11/20/2000
• Issued: 09/03/2002
• Est. Priority Date: 11/20/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Saripella, Satish C.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): TRAN, ANH Q
• Application Number:
  US09/716,526
• Time in Patent Office: 652 Days
• Field of Search: 326/33, 326/34, 326/83, 326/88, 326/92, 327/157, 327/156, 327/534, 327/537, 327/536, 327/543, 327/589
• US Class Current: 326/83
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence

Abstract

An apparatus comprising a pullup circuit, a pulldown circuit, and a control circuit. The pullup circuit may be configured to receive a first and second control signal. The pulldown circuit may be configured to receive a third and fourth control signal. The control circuit may be configured to generate the first, second, third and fourth control signals. The control circuit may comprise (i) a first and second control device coupled between the first and second control signals and a supply and (ii) a third and fourth control device coupled between the third and fourth control signals and the supply.

Claims

1. An apparatus comprises:

a pullup circuit configured to receive a first and second control signal;

a pulldown circuit configured to receive a third and fourth control signal; and

a control circuit configured to generate said first, second, third and fourth control signals, wherein said control circuit comprises (i) a first control device configured to generate said first control signal in response to a supply voltage, (ii) a second control device configured to generate said second control signal in response to said first control signal and said supply voltage, (iii) a third control device configured to generate said third control signal in response to said supply voltage and (iv) a fourth control device configured to generate said fourth control signal in response to said third control signal and said supply voltage.

2. The apparatus according to claim 1, wherein said apparatus is configured to provide current matching between said pullup circuit and said pulldown circuit.

3. The apparatus according to claim 1, wherein said apparatus is configured to provide accurate tracking between a reference device and a mirror device.

4. The apparatus according to claim 1, wherein said apparatus is configured to provide low output voltage compliance.

5. The apparatus according to claim 1, wherein said apparatus comprises a current reference circuit.

6. The apparatus according to claim 1, wherein said apparatus is configured to provide a constant current source.

7. The apparatus according to claim 1, wherein said apparatus is implemented within a charge pump of a phase lock loop (PLL).

8. The apparatus according to claim 1, wherein said apparatus is configured to improve a static phase offset specification in a single ended charge pump.

9. The apparatus according to claim 1, wherein:

said first and second control devices comprise one or more PMOS devices; and

said third and fourth control devices comprise one or more NMOS devices.

10. The apparatus according to claim 1, wherein said first control signal comprises a bias signal.

11. The apparatus according to claim 10, wherein said third control signal comprises a bias signal.

12. The apparatus according to claim 1, wherein:

said first and second control devices comprise one or more PMOS transistors that are equally sized; and

said third and fourth control devices comprise one or more NMOS transistors that are equally sized.

15. The apparatus according to claim 12, wherein said control devices are sized larger than devices of said pullup circuit and said pulldown circuit.

16. The apparatus according to claim 15, wherein said control devices have a channel width-to-length ratio that is four times a channel width-to-length ratio of said devices of said pullup and pulldown circuits.

17. The apparatus according to claim 1, wherein said second control device comprises:

a first transistor configured to receive said supply voltage at a first terminal and said first control signal at a second terminal; and

a second transistor having a first terminal connected to a third terminal of said first transistor and a second and third terminal connected together and configured to present said second control signal.

18. The apparatus according to claim 1, wherein said third control device comprises:

a first transistor configured to receive said supply voltage at a first terminal and said third control signal at a second terminal; and

a second transistor having a first terminal connected to a third terminal of said first transistor and a second and third terminal connected together and configured to present said fourth control signal.

13. An apparatus comprises:

a pullup circuit configured to receive a first and second control signal;

a pulldown circuit configured to receive a third and fourth control signal; and

means for generating said first, second, third and fourth control signals, wherein said generating means comprises (i) a first control device configured to generate said first control signal in response to a supply voltage, (ii) a second control device configured to generate said second control signal in response to said first control signal and said supply voltage, (iii) a third control device configured to generate said third control signal in response to said supply voltage and (iv) a fourth control device configured to generate said fourth control signal in response to said third control signal and said supply voltage.

14. A method for generating a constant current comprising the steps of:

(A) sourcing a current in response to a first and second control signal;

(B) sinking a current in response to a third and fourth control signal;

(C) generating (i) said first control signal in response to a supply voltage and (ii) said second control signal in response to said first control signal and said supply voltage; and

(D) generating (i) said third control signal in response to said supply voltage and (ii) said fourth control signal in response to said third control signal and said supply voltage.