Asymmetrical current steering output driver with compact dimensions

• US 6,445,241 B2
• Filed: 08/23/2001
• Issued: 09/03/2002
• Est. Priority Date: 05/29/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Gabara, Thaddeus John
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Nguyen, Hai L.
• Application Number:
  US09/935,814
• Publication Number:
  US 20020011892A1
• Time in Patent Office: 376 Days
• Field of Search: 327/403, 327/404, 327/493, 327/308, 327/518, 327/520, 327/511, 327/108, 323/311, 323/312, 323/315
• US Class Current: 327/404
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/017581 programmable

Abstract

A current output circuit with two output nodes connectable to a load and providing a plurality of discretely selectable current output magnitudes is provided. The circuit consists of a current driver attached across the output nodes supplying a particular current and one or more bypass resistors connected in parallel with the output nodes that can be switched between a non-conducting state and a resistive conducting state. When a load is connected across said output nodes, the particular magnitude of current sourced through the load can be selected by switching the state of the bypass resistors. The magnitude of the bypass resistors is preselected to provide several discretely selectable states of output current of substantial equal steps. The current driver can be combined with a current switch to increase the number of output states. Several current drivers with current switches may be provided and the bypass resistors integrated into the current switch itself.

Claims

1. An integrated circuit including a current output circuit having first and second output nodes connectable to a load, said output circuit comprising:

a plurality of current drivers; and

a plurality of current switches, each said current switch associated with a respective current driver for connecting the output of the respective current driver to at least one output node, each said current switch comprising first and second switches forming a first switch pair having a particular resistance when conducting, and third and fourth switches forming a second switch pair having substantially said particular resistance when conducting;

each said current switch having at least three states, wherein

in the first state, said first switch pairs being closed and said second switch pairs being open to connect the respective current driver of the current switch to said output nodes, whereby current flows from said first output node through the load, when connected, and into said second output node;

in the second state, said first switch pairs being open and said second switch pairs being closed to connect the respective current driver of the current switch to said output nodes, whereby current flows from said second output node through the load, when connected, and into said first output node; and

in the third state, both said first and second switch pairs being closed to thereby introduce a resistance in parallel with said load, when connected, the net current through said connected load from said respective current driver being substantially zero.

2. The circuit of claim 1, wherein each of said current drivers supplies a current of a different magnitude.

3. The circuit of claim 1, further comprising a control circuit receiving digital data as input and providing output signals to control the states of said switch pairs in said plurality of current switches.

4. The circuit of claim 1, wherein each of said first through fourth switches in said current switches is an MOS transistor.

5. The circuit of claim 4, wherein each said MOS transistor has a control signal appearing at the gate thereof, said MOS transistor being non-conducting when the magnitude of said control signal is a first voltage, said MOS transistor being conducting and having a particular predetermined resistance when said control signal is a second voltage.

6. The circuit of claim 5, wherein said MOS transistors forming said first through fourth switches in one of said current switches are scaled versions of corresponding MOS transistors forming first through fourth switches in a second one of said current switches, each of the control signals for said scaled MOS transistors being switchable between substantially the same first and second voltage magnitudes as the control signals for said corresponding MOS transistors.

7. The circuit of claim 6, further comprising:

a control circuit receiving digital data as input and providing output signals to control the states of said switch pairs in each one of said current switches.

8. An integrated circuit as claimed in claim 1 wherein a said current source comprises:

a current source including an MOS transistor biased to a source reference voltage;

a current sink including an MOS transistor biased to a sink reference voltage;

and a said current switch comprises a resistive current switch connecting said current source and said current sink of the corresponding switch to said first and second output nodes, said current switch including;

a first MOS transistor connected between said current source and said first output node;

a second MOS transistor connected between said second output node and said current sink;

a third MOS transistor connected between said current source and second output node; and

a fourth MOS transistor connected between said first output node and said current sink;

a first control signal connected to the gates of said first and second transistors;

a second control signal connected to the gates of said third and fourth transistors;

said transistors in each one of said drivers being scaled versions of corresponding transistors in each other one of said drivers;

said controlled first and second transistors being non-conducting when said first control signal is at a first voltage and being resistively conducting when said first control signal is at a second voltage;

said controlled third and fourth transistors being non-conducting when said second control signal is at substantially said first voltage and being resistively conducting when said second control signal is substantially said second voltage.

9. The circuit of claim 8, further comprising means for generating said source and sink reference voltages.

10. The circuit of claim 8, further comprising a control circuit receiving digital data as input and providing said first and second control signals for each of said drivers.

11. A current output circuit for an integrated circuit, said output circuit comprising:

first and second output nodes connectable to a load;

a current driver and

a current switch associated with said current driver for connecting the current driver to at least one output node, said current switch comprising first and second switches forming a first switch pair having a particular resistance when conducting and third and fourth switches forming a second switch pair having substantially said particular resistance when conducting;

said current switch have three states, wherein

in the first state, said first switch pairs being closed and said second switch pairs being open to connect said current driver to said output nodes, whereby current flows from said first output node through the load, when connected, and into said second output node;

in the second state, said first switch pairs being open and said second switch pairs being closed to connect said current driver to said output nodes, whereby current flows from said second output node through the load, when connected, and into said first output node; and

in the third state, both said first and second switch pairs being closed to thereby introduce a resistance in parallel with said load, when connected, the net current through said connected load from said respective current driver being substantially zero.