Self-controlled high efficiency power amplifier

• US 6,445,247 B1
• Filed: 06/01/2001
• Issued: 09/03/2002
• Est. Priority Date: 06/01/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Walker, Gordon Kent
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/872,845
• Time in Patent Office: 459 Days
• Field of Search: 330/10, 330/129, 330/136, 330/285
• US Class Current: 330/10
• CPC Class Codes: H03F 1/0222 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0266 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 2203/7239 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers and shunting lines by one or more switch(es)

Abstract

A novel and improved circuit and method for amplifying an input signal. The circuit includes an amplifier circuit having an input for receiving the input signal, and an amplifier control circuit, coupled to the amplifier circuit, for varying a supply power and a device periphery of the amplifier circuit in response to an amplitude envelope of the input signal. In this manner, the amplifier control circuit can control the linearity and the efficiency of the amplifier circuit using the characteristics of the input signal itself, without relying on any external processing.

Claims

1. A circuit comprising:

an amplifier circuit having an input for receiving an input signal; and

an amplifier control circuit for varying a supply power and a device periphery of the amplifier circuit in response to an amplitude envelope of the input signal, the amplifier control circuit having;

an envelope detector for detecting the input signal amplitude envelope, and for generating an envelope detection signal in response thereto;

at least one threshold detector, coupled to the envelope detector, for comparing the envelope detection signal to a threshold, and for generating a threshold comparison signal in response thereto;

an amplitude-modulation (AM) detector, coupled to the envelope detector, for detecting amplitude modulation of the input signal, and for generating a mode detection signal in response thereto; and

at least one power regulator, coupled to the at least one threshold detector and the AM detector, for varying the supply power in response to the threshold comparison signal and the mode detection signal.

2. The circuit of claim 1, wherein the amplifier circuit includes a first amplifier stage and a second amplifier stage coupled thereto, the amplifier control circuit variying the device periphery of the amplifier circuit by independently enabling and disabling the first amplifier stage and the second amplifier stage.

3. The circuit of claim 1, wherein the first and second amplifier stages are coupled in a cascade configuration.

4. The circuit of claim 3, wherein the amplifier circuit further comprises a first bypass switch, coupled to the first amplifier stage and the second amplifier stage and interposed therebetween, for bypassing the second amplifier stage in response to the threshold comparison signal and the mode detection signal.

5. The circuit of claim 4, wherein the amplifier circuit further comprises:

an output matching network, coupled to an output of the amplifier circuit; and

a second bypass switch, coupled to the first bypass switch and the output matching network and interposed therebetween.

6. The circuit of claim 3, wherein the second amplifier stage comprises a feedthrough amplifier.

7. The circuit of claim 6, wherein the feedthrough amplifier comprises:

an amplifier, and

a feedback network, coupled in parallel with the amplifier, such that signals incident at an input of the amplifier are conducted through the feedback network to an output of the amplifier.

8. The circuit of claim 2, wherein the first and second amplifier stages are coupled in a parallel configuration.

9. The circuit of claim 8, wherein the amplifier control circuit further comprises a DC bias control circuit, coupled to the AM detector and the at least one threshold detector, the DC bias control circuit for selectively applying a DC bias voltage to an input of the first amplifier stage and to an input of the second amplifier stage in response to the threshold comparison signal and the mode detection signal.

10. A method of amplifying an input signal in a circuit having an amplifier circuit controlled by an amplifier control circuit, the method comprising:

detecting an amplitude envelope of the input signal;

comparing the input signal amplitude envelope to a threshold;

varying a device periphery of the amplifier circuit in response to the comparing;

identifying a presence of amplitude-modulation (AM) in the input signal amplitude envelope; and

varying a power supply to the amplifier circuit in response to the presence of AM.

11. The method of claim 10, wherein varying the device periphery comprises:

increasing the device periphery when the input signal amplitude envelope is greater than or equal to the threshold; and

decreasing the device periphery when the input signal amplitude envelope is less than the threshold.

12. The method of claim 10, wherein varying the power supply comprises:

increasing the power supply when AM is present in the input signal amplitude envelope; and

decreasing the power supply when AM is not present in the input signal amplitude envelope.

13. The method of claim 10, wherein the amplifier circuit comprises first and second amplifier stages and wherein varying the device periphery comprises independently enabling and disabling the first and second amplifier stages.

14. The method of claim 13, wherein the first and second amplifier stages are coupled in a cascade configuration and wherein varying the device periphery further comprises bypassing the second amplifier stage.

15. The method of claim 13, wherein the first and second amplifier stages are coupled in a parallel configuration and wherein varying the device periphery further comprises selectively applying a DC bias voltage to an input of the first amplifier stage and an input of the second amplifier stage.