Method for carrying out a burn-in process for electrically stressing a semiconductor memory

• US 6,445,630 B2
• Filed: 03/23/2001
• Issued: 09/03/2002
• Est. Priority Date: 03/23/2000
• Status: Expired due to Term

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Ayadi, Kamel, Oezoguz-Geissler, Nedim, Lindolf, Jürgen
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/816,924
• Publication Number:
  US 20010033518A1
• Time in Patent Office: 529 Days
• Field of Search: 365/201, 365/149
• US Class Current: 365/201
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A circuit configuration is described that has a first voltage terminal, a second voltage terminal and a control input. A reference-ground potential is applied to the first voltage terminal and an operating voltage is applied to the second voltage terminal. The control input is supplied with a control voltage, the control voltage assumes voltage values which alternate between the reference-ground potential and the operating voltage. The alternation of the control voltage has the effect that components such as transistors and inverter that are present in the circuit configuration are active and thereby experience an accelerated aging process in order to stabilize the threshold voltage of the MOS transistor.

Claims

1. A method for carrying out a burn-in process for electrically stressing semiconductor components, which comprises the steps of:

providing a semiconductor component having a circuit configuration with a first voltage terminal, a second voltage terminal, a control input, and a MOS transistor;

applying a reference-ground potential to the first voltage terminal;

applying a second voltage to the second voltage terminal;

applying a control voltage to the control input, and varying the control voltage; and

setting the second voltage to alternate at a first frequency and the control voltage to alternate at a second frequency between the reference-ground potential and an operating voltage.

2. The method according to claim 1, which comprises providing the control voltage with voltage values which alternate between the reference-ground potential and an operating voltage.

3. The method according to claim 1, wherein the MOS transistor is part of a logic gate, the control input is a logic gate input, the first voltage terminal is a first logic gate voltage supply, and the second voltage terminal is a second logic gate voltage supply.

4. The method according to claim 1, which comprises setting the second voltage to a value of an operating voltage.

5. The method according to claim 1, which comprises setting the second voltage present at the second voltage terminal to alternate between the reference-ground potential and an operating voltage.

6. The method according to claim 1, which comprises setting the first frequency to be equal to the second frequency, and the first voltage and the second voltage have a phase difference of between 150 and 210 degrees.

7. The method according to claim 6, which comprises varying the phase difference.