Apparatus for processing and generating data using a digital signal processor

• US 6,445,699 B1
• Filed: 08/25/1999
• Issued: 09/03/2002
• Est. Priority Date: 02/25/1997
• Status: Expired due to Term

• Current Assignee: Lantiq Beteiligungs-GmbH & Company KG (Intel Corporation)
• Original Assignee: Siemens AG
• Inventors: Karmazin, Pavel
• Primary Examiner(s): Yao, Kwang Bin
• Assistant Examiner(s): Harper, Kevin C.
• Application Number:
  US09/382,529
• Time in Patent Office: 1,105 Days
• Field of Search: 710/52, 710/53, 710/71, 370/359, 370/366, 370/412, 370/413, 370/419, 370/474, 370/354, 370/435, 370/351, 370/357
• US Class Current: 370/359
• CPC Class Codes: H04Q 11/0407 using a stored programme control
• CPC Class Codes: H04Q 11/0471 Terminal access circuits
• CPC Class Codes: H04Q 2213/13034 A/D conversion, code compression/expansion
• CPC Class Codes: H04Q 2213/13036 Serial/parallel conversion, parallel bit transmission
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/13106 Microprocessor, CPU
• CPC Class Codes: H04Q 2213/13107 Control equipment for a part of the connection, distributed control, co-processing
• CPC Class Codes: H04Q 2213/13176 Common channel signaling, CCS7
• CPC Class Codes: H04Q 2213/13178 Control signals
• CPC Class Codes: H04Q 2213/13179 Fax, still picture
• CPC Class Codes: H04Q 2213/1318 Ringing
• CPC Class Codes: H04Q 2213/13209 ISDN
• CPC Class Codes: H04Q 2213/13216 Code signals, frame structure
• CPC Class Codes: H04Q 2213/1322 PBX
• CPC Class Codes: H04Q 2213/1324 Conference call
• CPC Class Codes: H04Q 2213/13396 Signaling in general, in-band signalling

Abstract

The invention describes a method and apparatus for processing and generating data using a digital signal processor. An interface unit for the signal processor is provided that reads in and preprocesses the data to be processed and/or data required for processing and/or generating data and supplies the data for pickup by the signal processor. Also, data which the signal processor processes or generates and supplies for pickup are postprocessed and output by the interface unit.

Claims

1. An apparatus for processing and generating data, comprising:

a digital signal processor; and

an interface unit connected to said digital signal processor, said interface unit being adapted to read in and preprocess data for said signal processor and to postprocess and output data from said digital signal processor;

said interface unit including a preprocessing and post-processing device for preprocessing and postprocessing the data, and a memory device connected to said preprocessing and postprocessing device and to said digital signal processor;

said preprocessing and postprocessing device including an expansion/compression device adapted to expand input data and to compress output data;

said memory device being divided into four memory areas including two memory areas reserved for write access by said preprocessing and postprocessing device and for read access by said digital signal processor, and two memory areas reserved for write access by said digital signal processor and for read access by said preprocessing and postprocessing device; and

wherein said digital signal processor is an ISDN processor and the apparatus is an integral part of an ISDN switching system.

2. The apparatus according to claim 1, wherein said two memory areas reserved for write access by said preprocessing and postprocessing device and for read access by said digital signal processor include a first memory area reserved for write access and a second memory area reserved for read access, and said first and second memory areas are interchanged cyclically during operation.

3. The apparatus according to claim 2, wherein said two memory areas reserved for write access by said digital signal processor and for read access by said preprocessing and postprocessing device include a third memory area reserved for write access by said signal digital processor and a fourth memory area reserved for read access by said preprocessing and postprocessing device, and said third and fourth memory areas are interchanged cyclically during operation.

4. The apparatus according to claim 1, wherein said two memory areas reserved for write access by said digital signal processor and for read access by said preprocessing and postprocessing device include a third memory area reserved for write access by said digital signal processor and a fourth memory area reserved for read access by said preprocessing and postprocessing device, and said third and fourth memory areas are interchanged cyclically during operation.

5. The apparatus according to claim 1, wherein said memory areas of said memory device are dimensioned to store therein decompressed data in an IOM-2 frame.

11. The apparatus according to claim 1, wherein said expansion/compression device expands and compresses data using tables stored in a read-only memory device.

6. An apparatus for processing and generating data, comprising:

only a single digital signal processor;

an interface unit connected to said digital signal processor, said interface unit being adapted to read in and preprocess data for said signal processor and to postprocess and output data from said digital signal processor;

said interface unit including a preprocessing and post-processing device for preprocessing and postprocessing the data, and a memory device connected to said preprocessing and postprocessing device and to said digital signal processor;

said preprocessing and postprocessing device including an expansion/compression device adapted to expand input data and to compress output data;

said memory device being divided into four memory areas including two memory areas reserved for write access by said preprocessing and postprocessing device and for read access by said digital signal processor, and two memory areas reserved for write access by said digital signal processor and for read access by said preprocessing and postprocessing device.

7. The apparatus according to claim 6, wherein said two memory areas reserved for write access by said preprocessing and postprocessing device and for read access by said digital signal processor include a first memory area reserved for write access and a second memory area reserved for read access, and said first and second memory areas are interchanged cyclically during operation.

8. The apparatus according to claim 6, wherein said two memory areas reserved for write access by said digital signal processor and for read access by said preprocessing and postprocessing device include a third memory area reserved for write access by said digital signal processor and a fourth memory area reserved for read access by said preprocessing and postprocessing device, and said third and fourth memory areas are interchanged cyclically during operation.

9. An apparatus for processing and generating data, comprising:

a digital signal processor;

an interface unit connected to said digital signal processor, said interface unit being adapted to read in and preprocess data for said signal processor and to postprocess and output data from said digital signal processor;

said interface unit including a preprocessing and post-processing device for preprocessing and postprocessing the data, and a memory device connected to said preprocessing and postprocessing device and to said digital signal processor;

said preprocessing and postprocessing device including an expansion/compression device adapted to expand input data and to compress output data;

said preprocessing and postprocessing device including a serial/parallel converter for converting serial input data to parallel data;

said memory device being divided into four memory areas including two memory areas reserved for write access by said preprocessing and postprocessing device and for read access by said digital signal processor, and two memory areas reserved for write access by said digital signal processor and for read access by said preprocessing and postprocessing device.

10. An apparatus for processing and generating data, comprising:

a digital signal processor;

an interface unit connected to said digital signal processor, said interface unit being adapted to read in and preprocess data for said signal processor and to postprocess and output data from said digital signal processor;

said interface unit including a preprocessing and post-processing device for preprocessing and postprocessing the data, and a memory device connected to said preprocessing and postprocessing device and to said digital signal processor;

said preprocessing and postprocessing device including an expansion/compression device adapted to expand input data and to compress output data;

said preprocessing and postprocessing device including a parallel/serial converter for converting parallel input data to serial data;

said memory device being divided into four memory areas including two memory areas reserved for write access by said preprocessing and postprocessing device and for read access by said digital signal processor, and two memory areas reserved for write access by said digital signal processor and for read access by said preprocessing and postprocessing device.