Memory controller in a multi-port bridge for a local area network
First Claim
1. A memory controller for providing an interface between a memory device and a communication bus in a multi-port bridge for a local area network wherein the communication bus interconnects a plurality of ports of the multi-port bridge, the memory controller comprising:
- a. a command decoder coupled to the communication bus for receiving bus commands from the communication bus and for forming an operation control signal indicative of a type of bus command received;
b. a memory control finite state machine coupled to receive the operation control signal from the command decoder, the memory control finite state machine having a plurality of states;
c. means for forming a plurality of memory control signals according to a current state of the memory control finite state machine wherein the memory control signals are coupled to control inputs of the memory device; and
d. means for forming row and column addresses according to memory address data received from the communication bus, the row and column addresses for coupling to address inputs of the memory device.
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Accused Products
Abstract
A memory controller in a multi-port bridge for a local area network. The multi-port bridge includes a switch engine, a memory and a plurality of ports, all of which are interconnected by a high speed communication bus. The memory includes look-up tables utilized for appropriately directing data packets among the ports, packet buffers utilized for temporarily storing packets and mailboxes for providing an interface between the switch engine and an external processor. The switch engine includes the memory controller, a bus controller and a look-up controller, each preferably including a finite state machine. The memory controller provides an interface between the memory and the communication bus by including a command decoder for decoding bus commands received from the communication bus. For example, the command decoder provides a response to memory read and write bus commands. In addition, the memory controller includes a memory control finite state machine for controlling operation of the memory controller according to the bus commands received from the command decoder. The memory controller also includes logic and address registers for providing appropriate row and column addresses to the memory device according to a current state of the memory control finite state machine. Because the memory control finite state machine controls operation of the memory controller, memory read and write operations are performed with a minimum of delay, thereby increasing the throughput capacity of the multi-port bridge.
111 Citations
28 Claims
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1. A memory controller for providing an interface between a memory device and a communication bus in a multi-port bridge for a local area network wherein the communication bus interconnects a plurality of ports of the multi-port bridge, the memory controller comprising:
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a. a command decoder coupled to the communication bus for receiving bus commands from the communication bus and for forming an operation control signal indicative of a type of bus command received;
b. a memory control finite state machine coupled to receive the operation control signal from the command decoder, the memory control finite state machine having a plurality of states;
c. means for forming a plurality of memory control signals according to a current state of the memory control finite state machine wherein the memory control signals are coupled to control inputs of the memory device; and
d. means for forming row and column addresses according to memory address data received from the communication bus, the row and column addresses for coupling to address inputs of the memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
a. a plurality of states for initiating a read operation;
b. a plurality of states for initiating a write operation; and
c. a state for determining whether an active operation is a read operation or a write operation.
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14. The memory controller according to claim 13 wherein the finite state machine further comprises a plurality of states for periodically refreshing the memory device.
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15. The memory controller according to claim 13 wherein the finite state machine further comprises a state for initiating a read or a write operation and wherein the state for initiating a read or a write operation occurs prior to the a state for determining whether an active operation is a read or a write operation.
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16. The memory controller according to claim 13 wherein a selected row in the memory device is activated in the state for initiating a read or a write operation.
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17. The memory controller according to claim 16 wherein each read operation includes a selected number of memory transfers.
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18. The memory controller according to claim 17 wherein each read operation is performed while the memory device is configured in burst mode.
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19. The memory controller according to claim 18 wherein the memory device is arranged according to pages and wherein when a read operation encounters a page crossing, the read operation is halted by appropriately conditioning the memory control signals.
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20. The memory controller according to claim 16 wherein each write operation includes a selected number of memory transfers.
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21. The memory controller according to claim 20 wherein each write operation its performed while the memory device is configured in burst mode.
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22. The memory controller according to claim 21 wherein the memory device is arranged according to pages and wherein when a write operation encounters a page crossing, the read operation is halted by appropriately conditioning the memory control signals.
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23. A memory controller for providing an interface between a memory device and a communication bus in a multi-port bridge for a local area network wherein the communication bus interconnects a plurality of ports of the multi-port bridge, the memory controller comprising:
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a. a command decoder coupled to the communication bus for receiving bus commands from the communication bus and for forming a control signal indicative of a type of bus command received;
b. a memory control finite state machine coupled to receive the control signal indicative of a type of bus command received from the command decoder, the memory control finite state machine having a plurality of states wherein the memory control finite state machine includes a refresh finite state machine for refreshing the memory device wherein the refresh finite state machine periodically initiates a refresh operation by requesting a halt of activity on the communication bus. - View Dependent Claims (24, 25, 26, 27, 28)
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Specification