Detection of undesired connection between conductive structures within multiple layers on a semiconductor wafer

• US 6,448,098 B1
• Filed: 02/01/2000
• Issued: 09/10/2002
• Est. Priority Date: 07/14/1999
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Milor, Linda S.
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Maldonado, Julio J.
• Application Number:
  US09/495,844
• Time in Patent Office: 952 Days
• Field of Search: 438/5, 438/6, 438/7, 438/10, 438/11, 438/14, 438/15, 438/16, 438/17, 438/18, 438/128, 438/466, 438/384, 438/107, 438/210, 438/257, 438/773, 438/776, 438/324, 438/763, 438/765, 438/381, 257/48, 257/797, 257/401, 257/776, 257/773, 324/765, 324/763
• US Class Current: 438/17
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention is a device and method for detecting undesired connection between conductive structures within multiple layers on a semiconductor wafer during fabrication of an integrated circuit on the semiconductor wafer. The present invention includes a first conductive structure fabricated within a first layer on the semiconductor wafer and a second conductive structure fabricated within a second layer on the semiconductor wafer. The present invention also includes an interlevel of an insulating material disposed between the first layer and the second layer for separating the first layer from the second layer. The present invention further includes a contact structure of conductive material disposed within the interlevel of the insulating material. The contact structure is connected to the first conductive structure, and the contact structure becomes undesirably connected to the second conductive structure from at least one of: sufficient misalignment of at least one of the first layer, the second layer, and the interlevel of insulating material; sufficient proximity effect on at least one of the first conductive structure, the second conductive structure, and the contact structure; and sufficient defects in at least one of the second layer and the interlevel of insulating material. In addition, the present invention includes a detector for determining when the contact structure is undesirably connected to the second conductive structure. The first conductive structure may have a comb structure with a respective contact structure connected to each tooth of the comb structure. In that case, the second conductive structure surrounds three sides of the respective contact structure.

Claims

1. A method for detecting undesired connection between conductive structures within multiple layers on a semiconductor wafer during fabrication of an integrated circuit on said semiconductor wafer, said method including steps of:

A. fabricating a first conductive structure within a first layer on said semiconductor wafer, and forming said first conductive structure to have a comb structure with a plurality of teeth;

B. fabricating a second conductive structure within a second layer on said semiconductor wafer, and forming said second conductive structure to surround three sides of each of said plurality of teeth of said comb structure of said first conductive structure;

C. fabricating an interlevel of an insulating material disposed between said first layer and said second layer for separating said first layer from said second layer;

wherein said first layer, said second layer, and said interlevel of insulating material are comprised of three separate levels of insulating material with said first conductive structure being formed within a first level of insulating material, said second conductive structure being formed within a second level of insulating material, and said interlevel of insulating material being disposed between said first and second levels of insulating material;

D. fabricating a plurality of contact structures of conductive material formed within said interlevel of said insulating material, and forming each of said plurality of contact structures to be connected to a respective one of said plurality of teeth of said first conductive structure; and

E. detecting when any of said plurality of contact structures is undesirably connected to any portion of said second conductive structure when said first conductive structure is misaligned with respect to said second conductive structure in any of a plurality of dimensions.

2. The method of claim 1, wherein said contact structure is undesirably connected to said second conductive structure from at least one of:

sufficient misalignment of at least one of said first layer, said second layer, and said interlevel of insulating material;

sufficient proximity effect on at least one of said first conductive structure, said second conductive structure, and said contact structure; and

sufficient defects in at least one of said second layer and said interlevel of insulating material.

3. The method of claim 1, wherein said first conductive structure is a top conductive structure disposed within the first layer that is a top layer disposed further away from said semiconductor wafer than said second conductive structure that is a bottom conductive structure disposed within the second layer that is a bottom layer disposed closer to said semiconductor wafer.

4. The method of claim 1, wherein said second conductive structure is a top conductive structure disposed within the second layer that is a top layer that is disposed further away from said semiconductor wafer than said first conductive structure that is a bottom conductive structure disposed within the first layer that is a bottom layer disposed closer to said semiconductor wafer.

5. The method of claim 1, wherein said step E further includes steps of:

applying a voltage between said first conductive structure and said second conductive structure; and

measuring a current flowing through said first conductive structure and said second conductive structure from said voltage being applied between said first conductive structure and said second conductive structure;

and wherein said current is substantially zero when said contact structure is not connected to said second conductive structure;

and wherein said current is greater than zero when said contact structure is undesirably connected to said second conductive structure.

6. The method of claim 1, further including steps of:

fabricating a third conductive structure within said first layer on said semiconductor wafer, said third conductive structure being a copy of said first conductive structure that is rotated 90°

;

fabricating a fourth conductive structure within said second layer on said semiconductor wafer, said fourth conductive structure being a copy of said second conductive structure that is rotated 90°

;

fabricating a second contact structure of conductive material disposed within said interlevel of said insulating material, said second contact structure being connected to said third conductive structure; and

detecting when said second contact structure is undesirably connected to said fourth conductive structure.

7. The method of claim 1, wherein said first conductive structure is comprised of a selected one of metal, polysilicon, local interconnect, and a conductive active region within said semiconductor wafer, and wherein said second conductive structure is comprised of a selected one of metal, polysilicon, local interconnect and a conductive active region within said semiconductor wafer.

8. A method for detecting undesired connection between conductive structures within multiple layers on a semiconductor wafer during fabrication of an integrated circuit on said semiconductor wafer, said method including steps of:

A. fabricating a first conductive structure within a first layer on said semiconductor wafer, and forming said first conductive structure to have a comb structure with a plurality of teeth;

B. fabricating a second conductive structure within a second layer on said semiconductor wafer, and forming said second conductive structure to surround three sides of each of said plurality of teeth of said comb structure of said first conductive structure;

C. fabricating an interlevel of an insulating material disposed between said first layer and said second layer for separating said first layer from said second layer;

wherein said first layer, said second layer, and said interlevel of insulating material are comprised of three separate levels of insulating material with said first conductive structure being formed within a first level of insulating material, said second conductive structure being formed within a second level of insulating material, and said interlevel of insulating material being disposed between said first and second levels of insulating material;

D. fabricating a plurality of contact structures of conductive material formed within said interlevel of said insulating material, and forming each of said plurality of contact structures to be connected to a respective one of said plurality of teeth of said first conductive structure; and

E. detecting when any of said plurality of contact structures is undesirably connected to any portion of said second conductive structure when said first conductive structure is misaligned with respect to said second conductive structure in any of a plurality of dimensions, wherein said step E further includes steps of;

applying a voltage between said first conductive structure and said second conductive structure; and

measuring a current flowing through said first conductive structure and said second conductive structure from said voltage being applied between said first conductive structure and said second conductive structure;

and wherein said current is substantially zero when said contact structure is not connected to said second conductive structure;

and wherein said current is greater than zero when said contact structure is undesirably connected to said second conductive structure;

and wherein said contact structure is undesirably connected to said second conductive structure from at least one of;

sufficient misalignment of at least one of said first layer, said second layer, and said interlevel of insulating material;

sufficient proximity effect on at least one of said first conductive structure, said second conductive structure, and said contact structure; and

sufficient defects in at least one of said second layer and said interlevel of insulating material;

and wherein said first conductive structure is a top conductive structure disposed within the first layer that is a top layer disposed further away from said semiconductor wafer than said second conductive structure that is a bottom conductive structure disposed within the second layer that is a bottom layer disposed closer to said semiconductor wafer;

and wherein said first conductive structure is comprised of a selected one of metal, polysilicon, local interconnect, and a conductive active region within said semiconductor wafer, and wherein said second conductive structure is comprised of a selected one of metal, polysilicon, local interconnect and a conductive active region within said semiconductor wafer.