Laterally recessed tungsten silicide gate structure used with a self-aligned contact structure including a straight walled sidewall spacer while filling recess
First Claim
1. A method of forming a MOSFET device, on a semiconductor substrate, comprising sequential the steps of:
- forming silicon nitride capped, polycide gate structures, on an underlying gate insulator layer, with a polycide layer, of said silicon nitride capped, polycide gate structures, comprised of a metal silicide layer, underlying a silicon nitride capping layer, and overlying a polysilicon layer;
ion implanting a first conductivity imparting dopant, into a region of said semiconductor substrate, not covered by said silicon nitride capped, polycide gate structures, to create a lightly doped source/drain region;
forming a lateral recess in the sides of said metal silicide layer;
performing a thermal oxidation procedure at a temperature between about 750 to 900°
C. in an oxygen—
steam ambient, to form a straight walled silicon oxide spacer, with a straight walled profile, on the sides of said silicon nitride capped, polycide gate structures, with said straight walled silicon oxide spacer comprised of a thick silicon oxide component, at a thickness between about 100 to 400 Angstroms, filling said lateral recess, in said metal silicide layer, and comprised of a thin silicon oxide component, at a thickness between about 50 to 200 Angstroms, located on the sides of said polysilicon layer, and with said thermal oxidation procedure forming a silicon oxide layer, at a thickness between about 35 to 100 Angstroms, on the surface of said lightly doped source/drain region;
depositing a silicon nitride layer on said straight walled silicon oxide spacer;
anisotropic etching of said silicon nitride layer to create composite insulator spacers on the sides of said silicon nitride capped, polycide gate structures, with said composite insulator spacers comprised of said silicon nitride layer, on said straight walled silicon oxide spacer;
ion implanting a second conductivity imparting dopant, into a region of said semiconductor substrate, not covered by said silicon nitride capped, polycide gate structures, or by said composite insulator spacers, to create a heavily doped source/drain region;
forming a self-aligned contact opening, in an interlevel dielectric layer, exposing a top portion of silicon nitride capped, polycide gate structures, and exposing said heavily doped source/drain region, located between said silicon nitride capped, polycide gate structures; and
forming a self-aligned contact structure, in said self-aligned contact opening.
1 Assignment
0 Petitions
Accused Products
Abstract
A process for fabricating composite insulator spacers, comprised of an underlying silicon oxide sidewall layer, and an overlying silicon nitride layer, formed on the sides of a polycide gate structure, has been developed. The process features initially, laterally recessing the exposed sides of a tungsten silicide component, of the polycide gate structure, via use of a selective wet etch solution. A subsequent oxidation procedure, used to thermally grow the silicon oxide sidewall layer, results in a thick silicon oxide component, located on the recessed sides of the tungsten silicide layer, while a thinner silicon oxide component is formed on the sides of the polysilicon component, of the polycide gate structure. Deposition of a silicon nitride layer, followed by an anisotropic RIE procedure, are then used to form the composite insulator spacers, on the sides of the polycide gate structure.
-
Citations
19 Claims
-
1. A method of forming a MOSFET device, on a semiconductor substrate, comprising sequential the steps of:
-
forming silicon nitride capped, polycide gate structures, on an underlying gate insulator layer, with a polycide layer, of said silicon nitride capped, polycide gate structures, comprised of a metal silicide layer, underlying a silicon nitride capping layer, and overlying a polysilicon layer;
ion implanting a first conductivity imparting dopant, into a region of said semiconductor substrate, not covered by said silicon nitride capped, polycide gate structures, to create a lightly doped source/drain region;
forming a lateral recess in the sides of said metal silicide layer;
performing a thermal oxidation procedure at a temperature between about 750 to 900°
C. in an oxygen—
steam ambient, to form a straight walled silicon oxide spacer, with a straight walled profile, on the sides of said silicon nitride capped, polycide gate structures, with said straight walled silicon oxide spacer comprised of a thick silicon oxide component, at a thickness between about 100 to 400 Angstroms, filling said lateral recess, in said metal silicide layer, and comprised of a thin silicon oxide component, at a thickness between about 50 to 200 Angstroms, located on the sides of said polysilicon layer, and with said thermal oxidation procedure forming a silicon oxide layer, at a thickness between about 35 to 100 Angstroms, on the surface of said lightly doped source/drain region;
depositing a silicon nitride layer on said straight walled silicon oxide spacer;
anisotropic etching of said silicon nitride layer to create composite insulator spacers on the sides of said silicon nitride capped, polycide gate structures, with said composite insulator spacers comprised of said silicon nitride layer, on said straight walled silicon oxide spacer;
ion implanting a second conductivity imparting dopant, into a region of said semiconductor substrate, not covered by said silicon nitride capped, polycide gate structures, or by said composite insulator spacers, to create a heavily doped source/drain region;
forming a self-aligned contact opening, in an interlevel dielectric layer, exposing a top portion of silicon nitride capped, polycide gate structures, and exposing said heavily doped source/drain region, located between said silicon nitride capped, polycide gate structures; and
forming a self-aligned contact structure, in said self-aligned contact opening. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13)
-
-
12. A method of forming composite insulator spacers on the sides of silicon nitride capped, polycide gate structures, on a semiconductor substrate, comprised of a silicon nitride layer, on a thermally grown, straight walled silicon oxide spacer, and with the straight walled silicon oxide spacer comprised of a thick silicon oxide component, located in a lateral recess in a tungsten silicide component of said silicon nitride capped, polycide gate structures, and comprised of a thin silicon oxide component, located on the sides of a polysilicon component of said silicon nitride capped, polycide gate structures, comprising sequential the steps of:
-
growing a silicon dioxide gate insulator layer;
depositing an in situ doped, polysilicon layer;
depositing a tungsten silicide layer;
depositing a silicon nitride capping layer;
performing an anisotropic RIE procedure, creating said silicon nitride capped, polycide gate structures, on underlying, said silicon dioxide gate insulator layer, with said silicon nitride capped, polycide gate structures comprised of said silicon nitride capping layer, of said tungsten silicide layer, and of said in situ doped polysilicon layer;
ion implanting a first conductivity imparting dopant, into a region of said semiconductor substrate not covered by said silicon nitride capped, polycide gate structures, to create a lightly doped source/drain region;
performing a wet etch procedure, to selectively create said lateral recess between about 100 to 400 Angstroms in the sides of said tungsten silicide layer;
performing a thermal oxidation procedure in an oxygen—
steam ambient, at a temperature between about 750 to 900°
C., to form said straight walled silicon oxide spacer with a straight walled profile, comprised of said thick silicon oxide component, between about 100 to 400 Angstroms in thickness, located on the sides of said tungsten silicide layer, in said lateral recess, and comprised of said thin silicon oxide component, between about 50 to 200 Angstroms in thickness, located on the sides of said polysilicon layer, while growing a silicon oxide layer between about 35 to 100 Angstroms, on the top surface of said lightly doped source/drain region;
depositing a silicon nitride layer;
anisotropic etching of said silicon nitride layer to create said composite insulator spacers, on the sides of said silicon nitride capped, polycide gate structures, with said composite insulator spacers comprised of said silicon nitride layer, and comprised of underlying, said straight walled silicon oxide spacer;
ion implanting a second conductivity imparting dopant, into a region of said semiconductor substrate, not covered by said silicon nitride capped, polycide gate structures, or by said composite insulator spacers, creating a heavily doped source/drain region;
depositing an interlevel dielectric layer;
performing an anisotropic reactive ion etching (RIE), procedure, using C4F8 as an etchant, to define a self-aligned contact hole in said interlevel dielectric layer, exposing a portion of the top surface of said silicon nitride capped, polycide gate structures, and exposing said heavily doped source/drain region, located between said silicon nitride capped, polycide gate structures, with an etch rate ratio of said interlevel dielectric layer to said silicon nitride layer of about 15 to 1, using said anisotropic RIE procedure; and
forming a self-aligned, metal contact structure, in said self-aligned contact hole, contacting underlying, said heavily doped source/drain region. - View Dependent Claims (14, 15, 16, 17, 18, 19)
-
Specification