Wiring method for producing a vertical, integrated circuit structure and vertical, integrated circuit structure

• US 6,448,174 B1
• Filed: 10/05/2000
• Issued: 09/10/2002
• Est. Priority Date: 03/26/1998
• Status: Expired due to Term

• Current Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Ramm, Peter
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Simkovic, Viktor
• Application Number:
  US09/647,012
• Time in Patent Office: 705 Days
• Field of Search: 438/455-459, 438/462, 438/107-109, 438/118, 438/618, 438/622, 438/628, 438/629, 438/637, 438/644, 438/977
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention relates to a wiring method for vertical system integration. According to the method described in the invention, the individual component layers in different substrates are first processed independently of each other in accordance with the state of the art (DE 44 33 846 A1) and then assembled. First, via holes are opened up on the front side of the top substrate which preferably pass through all the component layers present. The top substrate is then thinned from the rear side as far as the via holes, after which a fully processed bottom substrate is joined to the top substrate. Next, the via holes are extended (so-called interchip via holes) as far as a metallized level of the bottom substrate and the contact between the top and bottom substrates is established (wiring). According to the present invention the wiring is carried out in a way which allows for a maximum density of the vertical contacts between the metallization of the top substrate and that of the bottom substrate.

Claims

1. A wiring method for producing a vertical integrated circuit structure with the steps for:

providing a first substrate, which contains, in the region of a first main area, one or more first layers with circuit structures and an uppermost flat metallizing surface;

opening of via holes in a first step to the region of the first main area of the first substrate;

providing a second substrate, which contains, in the region of a second main area, at least one layer with circuit structures, and at least one flat metallizing surface;

connecting the first substrate with the second substrate, such that the side of the first substrate which lies opposite that of the first main area, and the side of the second main area of the second substrate are guided together so as to be aligned;

opening, in a second step, the via holes that are present in the first substrate in a direct vertical line from the metallization area of the first substrate to a predetermined flat metallizing surface of the second substrate; and

creating an electrically conductive connection between the uppermost flat metallizing surface of the first substrate and the predetermined flat metallizing surface of the second substrate by way of via holes, such that these steps are performed in the sequence indicated, characterized by the fact that the opening of the via holes occurs in such a manner that the via holes abut the uppermost flat metallizing surface.

3. A process according to claim 1, further comprising:

connecting the first substrate with an auxiliary substrate on the side of the first main area prior to providing the second substrate; and

removing the auxiliary substrate after connecting the first substrate with the second substrate.

4. A process according to claim 3, characterized by the fact that the first substrate is connected to the auxiliary substrate by way of an adhesive layer.

5. A process according to claim 4, characterized by the fact that an adhesive layer that is passivating and/or planarizing is used.

6. A process according to claim 1, characterized by the fact that

in the region of the first main area of the first substrate, a first set of alignment marks is produced, which penetrate the first layers of the circuit structures,

the second substrate contains a second set of alignment marks in the region of the second main area, and

the guiding together, in alignment, of the first and second substrate is accomplished by means of split optics and by virtue of the alignment marks in the range of the visible spectrum.

7. A process according to claim 6, characterized by the fact that the first alignment marks are etched through the first layers of the circuit structures and the second alignment marks are metallic structures in the second flat metallizing surface of the second substrate.

8. A process according to claim 1, characterized by the fact that the opening of the via holes is accomplished by means of etching.

9. A process according to claim 1, characterized by the fact that the via holes are opened in such a way in the first step that they penetrate all first layers with circuit structures.

10. A process according to claim 9, characterized by the fact that the via holes in the first step are opened as far as a few micrometers below the first layers of the circuit structures.

11. A process according to claim 1, characterized by the fact that the first substrate is an SOI substrate.

12. A process according to claim 1, characterized by at least one step for thinning the first substrate before joining together with the second substrate.

13. A process according to claim 12, in which the via holes in the first step are opened as far as a few micrometers below the first layers of the circuit structures, characterized by the fact that the thinning of the first substrate occurs as far as the via holes.

14. A process according to claim 12, in which the first substrate is an SOI substrate, characterized by the fact that the via holes are opened in the first step as far as the oxide layer of the SOI substrate, and the thinning of the first substrate takes place as far as this oxide layer.

15. A process according to claim 12, characterized by the fact that the thinning of the first substrate occurs by means of etching, grinding, and/or chemo-mechanical polishing.

16. A process according to claim 1, characterized by the fact that the connecting of the substrates occurs by means of a transparent adhesive layer that is applied to the second main area of the second substrate and/or to the side of the first substrate that lies opposite the first main area.

17. A process according to claim 16, characterized by the fact that a passivating and/or planarizing adhesive layer is used.

18. A process according to claim 1, characterized by the fact that the creation of an electrically conductive connection between the first or uppermost flat metallizing surface of the first substrate and the predetermined flat metallizing surface of the second substrate comprises the following processing steps:

exposing a portion of the first or uppermost flat metallizing surface;

deposition of a connective material into the via holes and onto the surface of substrate stack;

removal of the connective material from the surface of the substrate stack;

selective application of a metallizing material between the portion of the first or uppermost flat metallizing surface and the connective material.

19. A process according to claim 1, characterized by the fact that the production of an electrically conductive connection between the first or uppermost flat metallizing surface of the first substrate and the predetermined flat metallizing surface of the second substrate comprises the following processing steps:

deposition of a connection material into the via holes and onto the surface of the substrate stack;

removal of the connection material from the surface of the substrate stack;

partial exposure of parts of the first or uppermost flat metallizing surface; and

selective application of a metallizing material between the parts of the first flat metallizing surface and the connecting materials.

20. A process according to claim 18, characterized by the fact that the removal of the connection material occurs by means of chemical etching, mechanical and/or chemo-mechanical grinding.

21. A process according to claim 1, further comprising applying a passivating material creating the electrically conductive connection between the first or uppermost flat metallizing surface of the first substrate and predetermined flat metallizing surface of the second substrate.

22. A process according to claim 21, further comprising opening a connective opening to the metallizing material between the portion of the flat metallizing surface and the connection material after applying the passivating material.

23. A vertical, integrated circuit structure, characterized by the fact that it is produced by means of the process according to claim 1.

2. A wiring method for the production of a vertical integrated circuit structure with the steps for:

providing a first substrate, which contains, in the region of a first main area one or more first layers with circuit structures, and whose uppermost flat metallizing surface is not completed;

opening via holes in a first step in the region of the first main area of the first substrate;

providing a second substrate, which contains, in the region of a second main area, at least one layer with circuit structures and at least one flat metallizing surface;

connecting the first substrate with the second substrate, such that the side of the first substrate, which lies opposite the first main area, and the side of the second main area of the second substrate are guided together so as to be aligned;

opening, in a second step, the via holes that are present in the first substrate in a direct vertical line from the metallization area of the first substrate to a predetermined flat metallizing surface of the second substrate; and

introducing a metallic material into the via holes, as well as selective metallization of the surface, as a result of which an uppermost flat metallizing surface of the first substrate is brought into contact with the predetermined flat metallizing surface of the second substrate by means of the metallic material in the via holes, such that the opening of via holes occurs in such a manner that the via holes abut the uppermost flat metallizing surface and the steps are performed in the sequence that is indicated.

24. A process according to claim 2, characterized by:

connecting the first substrate with an auxiliary substrate on the side of the first main area prior to providing the second substrate and removing the auxiliary substrate after connecting the first substrate with the second substrate;

the fact that the first substrate is connected to the auxiliary substrate by way of an adhesive layer;

the fact that an adhesive layer that is passivating and/or planarizing is used;

the fact that

in the region of the first main area of the first substrate, a first set of alignment marks is produced, which penetrate the first layers of the circuit structures,

the second substrate contains a second set of alignment marks in the region of the second main area, and

the guiding together, in alignment, of the first and second substrate is accomplished by means of split optics and by virtue of the alignment marks in the range of the visible spectrum;

the fact that the first alignment marks are etched through the first layers of the circuit structures and the second alignment marks are metallic structures in the second flat metallizing surface of the second substrate;

the fact that the opening of the via holes is accomplished by means of etching;

the fact that the via holes are opened in such a way in the first step that they penetrate all first layers with circuit structures;

the fact that the via holes in the first step are opened as far as a few micrometers below the first layers of the circuit structures;

at least one step for thinning the first substrate before joining together with the second substrate.

25. A process according to claim 24, characterized by:

the fact that the first substrate is an SOI substrate;

the fact that either the via holes in the first step are opened as far as a few micrometers below the first layers of the circuit structures or that the via holes are opened in the first step as far as the oxide layer of the SOI substrate, and the thinning of the first substrate takes place as far as this oxide layer and characterized by the fact that the thinning of the first substrate occurs as far as the via holes;

the fact that the thinning of the first substrate occurs by means of etching, grinding, and/or chemo-mechanical polishing;

the fact that the connecting of the substrates occurs by means of a transparent adhesive layer that is applied to the second main area of the second substrate and/or to the side of the first substrate that lies opposite the first main area;

the fact that a passivating and/or planarizing adhesive layer is used.

26. A process according to claim 25, characterized by:

the fact that the creation of an electrically conductive connection between the first or uppermost flat metallizing surface of the first substrate and the predetermined flat metallizing surface of the second substrate comprises the following processing steps;

exposing a portion of the first or uppermost flat metallizing surface;

deposition of a connective material into the via holes and onto the surface of substrate stack;

removal of the connective material from the surface of the substrate stack;

selective application of a metallizing material between the portion of the first or uppermost flat metallizing surface and the connective material.

27. A process according to claim 25, characterized by:

the fact that the production of an electrically conductive connection between the first or uppermost flat metallizing surface of the first substrate and the predetermined flat metallizing surface of the second substrate comprises the following processing steps;

deposition of a connection material into the via holes and onto the surface of the substrate stack;

removal of the connection material from the surface of the substrate stack;

partial exposure of parts of the first or uppermost flat metallizing surface; and

selective application of a metallizing material between the parts of the flat metallizing surface and the connecting material.

28. A process according to claim 26, characterized by:

the fact that the removal of the connection material occurs by means of chemical etching, mechanical and/or chemo-mechanical grinding;

applying a passivating material after the step to create the electrically conductive connection between the first or uppermost flat metallizing surface of the first substrate and predetermined flat metallizing surface of the second substrate;

opening a connective opening to the metallizing material between the portion of the flat metallizing surface and the connection material after the step to apply the passivating material.

29. A process according to claim 27, characterized by:

the fact that the removal of the connection material occurs by means of chemical etching, mechanical and/or chemo-mechanical grinding;

applying a passivating material after the step to create the electrically conductive connection between the first or uppermost flat metallizing surface of the first substrate and predetermined flat metallizing surface of the second substrate;

opening a connective opening to the metallizing material between the portion of the flat metallizing surface and the connection material after the step to apply the passivating material.

30. A vertical, integrated circuit structure, characterized by the fact that it is produced by means of the process according to claim 28.

31. A vertical, integrated circuit structure, characterized by the fact that it is produced by means of the process according to claim 29.