Method for forming a high dielectric constant material

• US 6,448,192 B1
• Filed: 04/16/2001
• Issued: 09/10/2002
• Est. Priority Date: 04/16/2001
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kaushik, Vidya S.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): YEVSIKOV, VICTOR V
• Application Number:
  US09/835,770
• Time in Patent Office: 512 Days
• Field of Search: 438/785, 438/287, 438/591, 438/761, 438/762, 438/765, 438/770, 438/778, 438/779, 438/787
• US Class Current: 438/785
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28238 with sacrificial oxide
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence

Abstract

Highe quality silicon oxide having a plurality of monolayers is grown at a high temperature on a silicon substrate. A monolayer of silicon oxide is a single layer of silicon atoms and two oxygen atoms per silicon atom bonded thereto. The silicon oxide is etched one monolayer at a time until a desired thickness of the silicon layer is obtained. Each monolayer is removed by introducing a first gas to form a reaction layer on the silicon oxide. The gas is then purged. Then the reaction layer is activated by either another gas or heat. The reaction layer then acts to remove a single monolayer. This process is repeated until a desired amount of silicon oxide layer remains. Because this removal process is limited to removing one monolayer at a time, the removal of silicon oxide is well controlled. This allows for a precise amount of silicon oxide to remain.

Claims

1. A method for making a high dielectric constant gate dielectric on a semiconductor substrate:

forming a layer of a silicon oxide layer at a high temperature over a semiconductor substrate, wherein the silicon oxide layer comprises a plurality of monolayers of silicon dioxide;

removing a portion of the plurality of monolayers to leave at least one monolayer; and

depositing a layer of high dielectric constant material over the at least one monolayer, wherein the high dielectric constant material is not in contact with the semiconductor substrate.

2. The method of claim 1, wherein forming is performed at a temperature greater than about 850 degrees Celsius.

3. The method of claim 2, wherein forming is performed at a first temperature and removing is performed at a second temperature, wherein the second temperature is at least 650 degrees Celsius less than the first temperature.

4. The method of claim 3, wherein the high dielectric constant material comprises a material selected from hafnium oxide, zirconium oxide, zirconium aluminum oxide, and aluminum oxide.

5. The method of claim 4, wherein depositing is performed by atomic layer deposition.

6. The method of claim 5, further comprising placing the semiconductor substrate in a reaction chamber, and wherein removing further comprises:

introducing a first gas into the reaction chamber;

purging the reaction chamber of the first gas;

introducing a second gas into the reaction chamber to cause removing a first monolayer of the plurality of monolayers; and

repeating introducing the first gas, purging, and introducing the second gas until the portion of monolayers is removed.

7. The method of claim 6, wherein the first gas is CF₄, and the second gas is CHF₃.

8. The method of claim 6, wherein the first gas is selected from CF₄ and CHF₃, and the second gas is O₂.

9. The method of claim 5, further comprising placing the substrate in a reaction chamber, and wherein removing further comprises:

introducing a first gas into the reaction chamber;

purging the reaction chamber of the first gas;

heating the reaction chamber to cause the removing of a first monolayer of the plurality of monolayers; and

repeating introducing the first gas, purging, and heating until the portion of monolayers is removed.

10. A method for semiconductor processing, comprising:

providing a semiconductor substrate having a silicon oxide layer comprising a plurality of monolayers;

providing a reaction chamber;

placing the semiconductor substrate into the reaction chamber;

introducing a first gas into the reaction chamber;

purging the reaction chamber of the first gas;

introducing a second gas into the reaction chamber to cause removal of a first monolayer of the plurality of monolayers; and

repeating introducing the first gas, purging, and introducing the second gas until a predetermined amount of the silicon oxide layer is removed.

11. The method of claim 10, wherein the first gas is CF₄ and the second gas is CHF₃.

12. The method of claim 10, wherein the first gas is CF₄ and the second gas is O₂.

13. The method of claim 10, wherein the first gas is CHF₃ and the second gas is O₂.

14. A method for semiconductor processing, comprising:

providing a semiconductor substrate having a silicon oxide layer comprising a plurality of monolayers;

providing a reaction chamber;

placing the semiconductor substrate into the reaction chamber;

plurality of monolayers; and

repeating introducing the first gas, purging, and heating until a predetermined amount of the silicon dioxide layer is removed.

15. The method of claim 14, wherein the first gas is selected from HF and CCl₂F₂.

16. The method of claim 15, wherein the heating is by rapid thermal annealing.

17. A method of forming a transistor, comprising:

providing a semiconductor substrate;

providing a reaction chamber,

forming a semiconductor oxide on the substrate, wherein the semiconductor oxide layer comprises a plurality of monolayers;

placing the semiconductor substrate with the semiconductor oxide layer into the reaction chamber;

after inserting the semiconductor substrate into the reaction chamber, introducing a first gas into the reaction chamber;

purging the reaction chamber of the first gas;

after purging the reaction chamber, introducing a second gas into the reaction chamber to cause etching of a first monolayer of the plurality of monolayers;

repeating introducing the first gas, purging, and introducing the second gas until a predetermined amount of the semiconductor oxide layer is removed to leave an interfacial layer of semiconductor oxide layer on the semiconductor substrate;

depositing a layer of high dielectric constant material over the interfacial layer;

forming a gate electrode over the layer of high dielectric constant material; and

forming a source and a drain in the semiconductor substrate and adjacent to the gate electrode.

18. The method of claim 17, wherein the semiconductor substrate is silicon and the semiconductor oxide layer is silicon oxide.

19. The method of claim 18, wherein the first gas comprises a gas selected from CHF₃ and CF₄, and the second gas comprises O₂.

20. The method of claim 18, wherein the first gas is CHF₃, and the second gas is CF₄.

21. The method of claim 18, wherein the silicon oxide is formed at temperature of at least 850 degrees Celsius.

22. The method of claim 18, wherein introducing the first gas, purging, and introducing the second gas are performed at temperatures below 200 degrees Celsius.

23. The method of claim 18, wherein purging is performed by flowing a non-reactive gas over the substrate.

24. A method of forming a transistor, comprising:

providing a semiconductor substrate;

providing a reaction chamber,

forming a semiconductor oxide layer on the substrate, wherein the semiconductor oxide layer comprises a plurality of monolayers;

inserting the semiconductor substrate with the semiconductor oxide layer into the reaction chamber;

after inserting the semiconductor substrate into the reaction chamber, introducing a first gas into the reaction chamber;

purging the reaction chamber of the first gas;

after purging the reaction chamber, introducing a second gas into the reaction chamber to cause the etching of a first monolayer of the plurality of monolayers;

repeating introducing the first gas, purging, and introducing the second gas until a desired amount of the semiconductor oxide layer is removed to leave an interfacial layer of semiconductor oxide layer on the semiconductor surface;

depositing a layer of high dielectric constant material over the interfacial layer;

forming a gate electrode over the layer of high dielectric constant material; and

forming a source and a drain adjacent in the semiconductor substrate and adjacent to the gate electrode.

25. The method of claim 24, wherein the semiconductor substrate is silicon and the semiconductor oxide layer is silicon oxide.

26. The method of claim 25, wherein the first gas is selected from HF and CCl₂F₂.

27. The method of claim 25, wherein the heating is by rapid thermal annealing.

28. The method of claim 25, wherein the silicon oxide layer is formed at temperature of at least 850 degrees Celsius.

29. The method of claim 25, wherein introducing the first gas, purging, and heating the second gas are performed at temperatures below 200 degrees Celsius.

30. The method of claim 25, wherein purging is performed by flowing a non-reactive gas over the substrate.

31. The method of claim 25, wherein the silicon oxide layer is doped.

32. The method of claim 31, wherein the silicon oxide layer is doped with nitrogen.

33. A method for semiconductor processing, comprising:

providing a semiconductor substrate having a silicon oxide layer over the substrate, wherein the silicon oxide layer comprises a plurality of monolayers;

providing a reaction chamber;

inserting the semiconductor substrate into the reaction chamber;

introducing a first gas into the reaction chamber to form a reaction layer on the silicon oxide;

purging the reaction chamber of the first gas;

activating the reaction layer to remove a first monolayer of the plurality of monolayers; and

repeating introducing, purging, and activating until a desired portion of the silicon oxide layer has been removed.

34. The method of claim 33 wherein activating comprises introducing a second gas into the chamber.

35. The method of claim 34 further comprising depositing a layer of high dielectric constant material after repeating introducing purging, and activating until a predetermined portion of the silicon oxide layer is removed.

36. The method of claim 33 wherein activating comprises rapid thermal annealing the reaction layer.

37. The method of claim 36 further comprising depositing a layer of high dielectric constant material after repeating introducing purging, and activating until a predetermined portion of the silicon oxide layer is removed.