Substrate for electronic packaging, pin jig fixture

• US 6,448,510 B1
• Filed: 06/22/2000
• Issued: 09/10/2002
• Est. Priority Date: 05/20/1997
• Status: Expired due to Term

• Current Assignee: Micro Components Ltd. (Simcoe Mining Resources, Inc.)
• Original Assignee: Micro Components Ltd. (Simcoe Mining Resources, Inc.)
• Inventors: Mirsky, Uri, Neftin, Shimon
• Primary Examiner(s): Cunio, Kamand
• Assistant Examiner(s): PATEL, ISHWARBHAI B
• Application Number:
  US09/424,179
• Time in Patent Office: 810 Days
• Field of Search: 174/263, 174/255, 174/256, 174/257, 174/258, 174/261, 174/262, 174/264, 174/265, 174/260, 174/52.4, 174/252, 174/266, 298/30, 298/46, 298/40, 298/52, 298/42, 298/43, 361/760, 361/803, 361/808, 361/809, 361/810, 361/717, 361/712, 361/713, 361/719, 361/720, 361/704, 361/707, 428/901, 428/209, 257/697, 257/699, 257/771, 257/770, 257/778, 257/765, 257/764, 257/700, 257/702, 257/737, 257/238
• US Class Current: 174/264
• CPC Class Codes: C25D 11/022 Anodisation on selected surface areas
• CPC Class Codes: C25D 11/04 of aluminium or alloys based thereon
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 2201/09827 Tapered, e.g. tapered hole, via or groove bevelled, chamferred or tapered edge H05K2201/09154
• CPC Class Codes: H05K 2203/0315 Oxidising metal
• CPC Class Codes: H05K 2203/0323 Working metal substrate or core, e.g. by etching, deforming
• CPC Class Codes: H05K 2203/1142 Conversion of conductive material into insulating material or into dissolvable compound
• CPC Class Codes: H05K 3/02 in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
• CPC Class Codes: H05K 3/445 having insulated holes or insulated via connections through the metal core
• CPC Class Codes: Y10S 428/901 Printed circuit
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A substrate for electronic packaging, the substrate having a discrete, generally prismatoid, initially electrically conductive valve metal solid body with one or more spaced apart, original valve metal vias each individually electrically islolated by a porous oxidized body portion therearound. A pin jig fixture for mechanically masking a metal surface, the pin jig fixture having an anodization resistant bed of pins each pin having a leading end surface for intimate juxtaposition against a metal surface to mask portions thereof.

Claims

1. A substrate for use in electronic packaging, the substrate consisting of a discrete, non-layered, solid body having a pair of generally parallel major surfaces and having one or more electrically insulated original valve metal vias substantially perpendicularly disposed to said major surfaces and at least partially surrounded by porous valve metal oxide based material, each via having exposed end surfaces substantially co-directional with said major surfaces, the substrate being formed only from a non-layered original valve metal solid blank having major surfaces with a distance therebetween equal to a distance between the substrate'"'"'s major surfaces, by a single process of porous anodization of said blank with the blank'"'"'s major surfaces being masked, at least one of the blank'"'"'s major surfaces being masked selectively, for converting portions of said blank that were non-masked at least at one of the blank'"'"'s major surfaces into porous valve metal oxide and thereby retaining portions of said blank that were masked at both of the blank'"'"'s major surfaces as said one or more electrically insulated original valve metal vias.

2. A substrate according to claim 1, wherein a via has a generally diverging cross section therealong and a maximum thickness between said end surfaces of between about 25 μ

m and about 150 μ

m.

3. A substrate according to claim 1, wherein a via has a barrel shaped cross section area therealong and a maximum thickness between said end surfaces of between about 25 μ

m and about 150 μ

m.

4. A substrate according to claims 1, 2 or 3, wherein said solid body has one or more recesses in one of said major surfaces inwardly extending toward the other of said major surfaces thereby forming a corresponding number of thin portions, at least one of said thin portions constituting an electrically insulated original valve metal via.

5. A substrate according to claim 4 wherein non-recessed portions have a thickness between said major surfaces from about 200 μ

m to about 10 mm.

6. A substrate according to claim 4 wherein a recess has a frusto-conical shape.

7. A substrate according to claim 1, wherein both major surfaces of said blank are masked selectively for said single process of porous anodization.

8. A process for manufacturing a substrate having a desired product specification for use in electronic packaging, the process consisting only of the steps of:

(a) providing a discrete valve metal non-layered solid blank having a pair of opposing generally parallel major surfaces;

(b) covering both said major surfaces of the non-layered solid blank with masks, in accordance with the desired product specification, at least one of said major surfaces being masked selectively;

(c) porously anodizing the masked non-layered solid blank for converting portions of said blank that were non-masked at least at one of the blank'"'"'s major surfaces into porous valve metal oxide material and thereby retaining portions of said blank that were masked at both said blank'"'"'s major surfaces as one or more electrically insulated original valve metal vias embedded in said porous valve metal oxide material; and

(d) removing said masks from both said major surfaces.

9. A process according to claim 8, wherein one major surface of the blank is fully masked, whereby the blank undergoes one-sided porous anodization, wherein a distance between the major surfaces of the blank has a maximal value between about 25 μ

m and about 150 μ

m.

10. A process according to claim 9, wherein said vias have a cross-sectional area diverging away from at least one of said major surfaces.

11. A process according to claim 8, wherein both said major surfaces of said blank are masked selectively, whereby the blank undergoes two-sided porous anodization, wherein a distance between the major surfaces of the blank has a maximal value between about 25 μ

m and about 300 μ

m.

12. A pin jig fixture for mechanically masking a metal surface, the pin jig fixture being connected to an electrical power source and comprising a bed of pins each having a leading end surface for intimate juxtaposition against the metal surface for masking a corresponding area thereof, one or more of said leading end surfaces being directly connected to the electrical power source for electrically connecting the electrical power source to the metal surface on intimate juxtaposition thereagainst.

13. A pin jig fixture according to claim 12 wherein said bed of pins is formed from an electrically conductive metal based material.

14. A pin jig fixture according to claim 13, wherein said bed of pins is formed from an anodization resistant valve metal based material.

15. A pin jig fixture according to claim 12, wherein the leading end surfaces of said bed of pins are substantially co-planar.

16. A pin jig fixture according to claim 12, wherein said pins are of two or more different lengths.

17. A process for preparing a selectively masked valve metal surface, the process comprising the steps of:

(a) providing a pin jig fixture comprising a bed of pins each having a leading end surface, one or more of said leading end surfaces being coupled with one or more electrical power source connection points;

(b) intimately juxtaposing the leading end surfaces of the bed of pins against a valve metal surface to mask a corresponding area of the valve metal surface;

(c) electrically connecting the pin jig fixture to an electrical power source, thereby electrically connecting the electrical power source to the corresponding masked area of the valve metal surface; and

(d) porously anodizing the valve metal surface.

18. A substrate for use in electronic packaging, the substrate comprising a discrete, non-layered solid body having a pair of generally parallel major surfaces and having one or more electrically insulated original valve metal vias diverging inwardly away from at least one of said major surfaces and at least partially surrounded by porous valve metal oxide based material, each via having exposed end surfaces substantially co-directional with said major surfaces, the substrate being form, only from an original valve metal non-layered solid blank by a single process of porous anodization of said blank.

19. A substrate according to claim 18, wherein said vias diverge inwardly away from both said major surfaces.