Temperature control structure

• US 6,448,575 B1
• Filed: 02/02/2000
• Issued: 09/10/2002
• Est. Priority Date: 10/08/1999
• Status: Expired due to Fees

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Slocum, Alexander H., Walker, Ernest P., Pfahnl, Andreas C., Sartschev, Ronald A.
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US09/497,010
• Time in Patent Office: 951 Days
• Field of Search: 324/760, 324/765, 219/497, 257/714, 257/707, 257/716, 257/48, 257/713, 118/724, 118/725, 438/715
• US Class Current: 257/48
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor structure for controlling the temperature of a component is described. The structure includes a resistive layer having one or more channels provided therein and having a resistance characteristic such that a signal applied thereto causes the resistive layer to generate heat. A cooling fluid is fed through the one or more channels to cool both the structure and a component disposed on the structure. By providing the cooling channels in the resistive layer, the heating and cooling sources are intermingled. The structure can optionally include precising and vacuum clamping structures, to locate and hold the component that is to be temperature controlled.

Claims

1. A temperature control structure comprising:

a first electrically insulating layer having first and second opposing surfaces;

a resistive layer having first and second opposing surfaces and having one or more channels provided therein wherein at least a portion of said resistive layer is doped with a dopant to a dopant concentration selected such that a signal applied to said resistive layer causes heat to be generated, with the first surface of said resistive layer disposed over the first surface of said first electrically insulating layer; and

a second electrically insulating layer having first and second opposing surfaces with the first surface of said second electrically insulating layer disposed over the second surface of said heat generating layer.

2. The device of claim 1 wherein:

said first and second electrically insulating layers are comprised of silicon dioxide; and

said resistive layer is comprised of a Group III-V material.

3. The device of claim 2 further comprising:

a top layer comprised of a Group III-V material, said top layer disposed on the second surface of said first electrically insulating layer; and

a bottom layer comprised of a Group III-V material , said bottom layer disposed on the second surface of said second electrically insulating layer.

4. The device of claim 3 further comprising an integrated circuit formed on at least one of said top and bottom layers.

5. The structure of claim 4 wherein:

said first and second layers are comprised of silicon oxide; and

said top and bottom layers are comprised of silicon.

6. The device of claim 1 wherein the portions of said resistive layer which have been doped comprise those portions outside of the channels provided in said resistive layer.

7. A temperature control structure comprising:

a first semiconductor layer and having first and second opposing surfaces and having one or more fluid channels provided therein with at least a portion of said first semiconductor layer being doped with a predetermined dopant to a predetermined dopant concentration; and

a second semiconductor layer having first and second opposing surfaces with the first surface of said first semiconductor layer disposed over the second surface of said second semiconductor layer, wherein at least a portion of said second semiconductor layer is doped with a predetermined dopant to a predetermined dopant concentration.

8. The structure of claim 7 wherein the first surface of said second semiconductor layer is provided having one or more fluid channels provided therein and wherein said first and second semiconductor layers are aligned such that the one or more fluid channels in said first semiconductor layer align with the one or more fluid channels in said second semiconductor layer.

9. The structure of claim 8 further comprising a third semiconductor layer having first and second opposing surfaces with the first surface disposed over the second surface of said first semiconductor layer and where said third semiconductor layer is provided having an insulating characteristic.

10. The structure of claim 9 wherein the first surface of said third semiconductor layer corresponds to an electrically insulating surface.

11. The structure of claim 10 wherein said electrically insulating surface is comprised of silicon dioxide.

12. The structure of claim 9 wherein the first, second and third semiconductor layers are provided as semiconductor wafers which are diffusion bonded to effectively provide the semiconductor structure as a monolithic semiconductor structure.

13. The structure of claim 12 wherein said first, second and third semiconductor layers are provided having a vacuum hole provided therein.

14. The structure of claim 13 wherein the second surface of said third semiconductor layer is provided having at least one vacuum channel in fluid communication with the vacuum hole.

15. The structure of claim 9 wherein portions of said first and second semiconductor layers are doped with a dopant such that said portions of said first and second layers correspond to conductive regions having a relatively high electrical resistance characteristic.

16. The structure of claim 15 further comprising a power source coupled to said first and second semiconductor layers.

17. A semiconductor device comprising:

a first layer having at least one integrated circuit formed thereon;

one or more electrically insulating layers disposed about said first layer;

one or more shielding layers disposed about said first layer;

one or more electrically resistive layers disposed over one of;

(1) said one or more electrically insulating layers or (2) said one or more shielding layers; and

one or more cooling layers with at least one of the at least or more cooling layers having one or more cooling channels provided therein with the cooling channels substantially coplanar with the resistive layers.

18. The semiconductor device of claim 17 wherein:

the integrated circuit formed on said first layer corresponds to one of;

a logic circuit or a memory circuit;

said one or more electrically insulating layers are disposed over said first layer; and

said one or more electrically resistive layers are disposed over said one or more electrically insulating layers and are provided having cooling passages therein.

19. The semiconductor device of claim 18 where at least one of said one or more insulative layers is adjacent to one of the one or more shielding layers.