Programmable chalcogenide fuse within a semiconductor device

• US 6,448,576 B1
• Filed: 08/30/2001
• Issued: 09/10/2002
• Est. Priority Date: 08/30/2001
• Status: Expired due to Term

• Current Assignee: Ovonyx Memory Technology, LLC
• Original Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Inventors: Rodgers, John C., Sturcken, Keith K., Spreen, Peter W., Shah, Tushar K., Davis, John D., McIntyre, Thomas J.
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): Wilson, Christian D.
• Application Number:
  US09/943,178
• Time in Patent Office: 376 Days
• Field of Search: 257/50, 257/529, 257/530, 257/209, 438/131, 438/132, 438/600, 438/601
• US Class Current: 257/50
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

Claims

1. A programmable fuse structure within a semiconductor device, said programmable fuse structure comprising:

a resistor located on a semiconductor substrate;

a chalcogenide fuse thermally coupled to said resistor to permit heat transfer therebetween; and

a conductive layer deposited on top of said chalcogenide fuse to form separate electrical connections to said chalcogenide fuse and said resistor, wherein said chalcogenide fuse can be toggled between an electrical conduction state and an electrical non-conduction state by supplying current pulses to said resistor to heat said resistor.

2. The programmable fuse structure of claim 1, wherein said resistor is a polysilicon resistor.

3. The programmable fuse structure of claim 1, wherein said conductive layer is an aluminum layer.

4. The programmable fuse structure of claim 3, wherein said conductive layer further includes a titanium and titanium nitride layer.

5. The programmable fuse structure of claim 1, wherein said programmable fuse structure further includes contacts through said conductive layer to connect to said chalcogenide fuse.

6. The programmable fuse structure of claim 1, wherein said programmable fuse structure further includes contacts through said conductive layer to connect to said resistor.

7. The programmable fuse structure of claim 1, wherein said electrical conduction state is a polycrystalline state and said electrical non-conduction state is an amorphous state.

8. A semiconductor device having a programmable fuse structure, said semiconductor device comprising:

a substrate;

a first pair of interconnects and a second pair of interconnects;

a resistor, located on top of said substrate, connected between said first pair of interconnects;

a chalcogenide fuse thermally coupled to said resistor to permit heat transfer therebetween, connected between said second pair of interconnects, wherein said chalcogenide fuse can be toggled between an electrical conduction state and an electrical non-conduction state by supplying current pulses to said resistor to heat said resistor.

9. The semiconductor device of claim 8, wherein said resistor is a polysilicon resistor.

10. The semiconductor device of claim 8, wherein said conductive layer is an aluminum layer.

11. The semiconductor device of claim 10, wherein said conductive layer further includes a titanium and titanium nitride layer.

12. The semiconductor device of claim 8, wherein said conductive layer connects between said first pair of interconnects through respective contacts.

13. The semiconductor device of claim 8, wherein said resistor connects between said second pair of interconnects through respective contacts.

14. The semiconductor device of claim 8, wherein said electrical conduction state is a polycrystalline state and said electrical non-conduction state is an amorphous state.