Reduced area storage node junction and fabrication process
First Claim
1. An active area section electrically connecting a gate to a capacitor, wherein the active area section is next to a field oxide, the active area section comprising:
- a first, region under the capacitor ranging from the field oxide toward the gate;
a second region ranging from the gate toward the field oxide such that the capacitor can be electrically connected to the second region of the active area, the second region having an impurity not found in the first region; and
a conductive diffusion barrier on at least that portion of the second region that will be connected to the capacitor.
0 Assignments
0 Petitions
Accused Products
Abstract
An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an anive area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region. The contact region has a first segment adjacent to the gate electrode and a second segment interposed between the first segment and the field oxide region. The first segment is thereby isolated from the field oxide region by the second segment. The first segment is doped to a second conductivity type. A layer of storage polysilicon is formed in electrical contact with the first segment of the contact region but not the second segment of the contact region. The storage polysilicon is isolated from the field oxide through an insulating layer interposed between the storage polysilicon and the second segment of the contact region.
-
Citations
10 Claims
-
1. An active area section electrically connecting a gate to a capacitor, wherein the active area section is next to a field oxide, the active area section comprising:
-
a first, region under the capacitor ranging from the field oxide toward the gate;
a second region ranging from the gate toward the field oxide such that the capacitor can be electrically connected to the second region of the active area, the second region having an impurity not found in the first region; and
a conductive diffusion barrier on at least that portion of the second region that will be connected to the capacitor. - View Dependent Claims (2, 3)
-
-
4. A region of a support structure, wherein the support structure is under a gate and a storage device, and wherein the region is next to an isolation structure and comprises:
-
an insulating spacer along the gate;
a first area next to the isolation structure and under the storage device;
a second area next to the first area and next to the gate at a location of an electrical junction between the storage device and the support structure, the second area extending under the spacer, the second area having a concentration of a first dopant greater than any concentration of the first dopant in the first area; and
metal overlaying the second area of the support structure. - View Dependent Claims (5, 6, 7, 10)
-
-
8. A memory cell environment, comprising:
-
a gate;
a source/drain area operatively associated with the gate;
a semiconductive area operatively associated with the source/drain area;
a non-conductive area operatively associated with the semiconductive area;
a capacitor over portions of the source/drain area, the semiconductive area and the non-conductive area. - View Dependent Claims (9)
-
Specification
-
- Resources
-
Current AssigneeMicron Technology, Inc.
-
Original AssigneeMicron Technology, Inc.
-
InventorsGonzalez, Fernando
-
Primary Examiner(s)Wilson, Allan R.
-
Application NumberUS09/738,413Publication NumberTime in Patent Office636 DaysField of Search257/296-313US Class Current257/306CPC Class CodesH10B 12/033 the capacitor extending ove...
