Semiconductor device, semiconductor device mounting structure, liquid crystal device, and electronic apparatus

• US 6,448,663 B1
• Filed: 03/03/2000
• Issued: 09/10/2002
• Est. Priority Date: 03/08/1999
• Status: Expired due to Term

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Uchiyama, Kenji
• Primary Examiner(s): Talbott, David L.
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/519,436
• Publication Number:
  US 20020100974A1
• Time in Patent Office: 921 Days
• Field of Search: 257/773, 257/776, 257/778, 257/780, 257/779, 257/789
• US Class Current: 257/778
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/838 Bonding techniques
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device, a mounting structure thereof, a liquid crystal device, and an electronic apparatus having an improved bump electrode structure, such that the bump electrodes and corresponding electrode terminals can be electrically connected through an anisotropic conductive film without compromising, or causing deterioration of, the electrical characteristics or reliability of the device, even when the bump electrodes are formed with a narrow pitch. Since the bump electrodes of the semiconductor device are tapered inward from top to bottom, the base portions of adjacent bump electrodes are spaced apart from each other by wider gaps than the corresponding upper portions. Thus, a large number of conductive particles in the conductive film do not gather between adjacent bump electrodes to cause short-circuiting therebetween. Further, since the upper portions of the bump electrodes are wider and the opposing surface areas of both the bump electrodes and the electrode terminals are relatively large, a large number of conductive particles are distributed between the bump electrodes and the electrode terminals. This ensures that the bump electrodes and the electrode terminals are electrically connected in a satisfactory manner. Therefore, with this arrangement, a high level of reliability can be achieved, even when the bump electrodes are formed in high density.

Claims

1. A semiconductor device, comprising:

a first substrate having a first edge and a second edge substantially perpendicular to the first edge;

a second substrate to which the first substrate is mounted;

a resin for bonding the first substrate and the second substrate together;

a plurality of conductive particles in the resin;

a plurality of first electrodes aligned with the first edge, each of the first electrodes having a base surface formed on the first substrate, an upper surface, and a pair of opposing side walls aligned with the second edge, wherein, for each of the first electrodes, the cross-sectional width between the pair of opposing side walls linearly decreases from the upper surface towards the base surface; and

a plurality of second electrodes aligned with the second edge, each of the second electrodes having a base surface formed on the first substrate, an upper surface, and a pair of opposing side walls aligned with the first edge, wherein, for each of the second electrodes, the cross-sectional width between the pair of opposing side walls linearly decreases from the upper surface towards the base surface;

wherein the resin is able to flow outwardly through gaps between adjacent first electrodes and gaps between adjacent second electrodes when the first substrate and the second substrate are bonded together.

2. The semiconductor device of claim 1, wherein the upper surface of each electrode has a width of between about 15 μ

m and about 20 μ

m.

3. The semiconductor device of claim 1, wherein the upper portions of adjacent first electrodes and the upper portions of adjacent second electrodes are separated from each other by a gap of between about 20 μ

m and about 25 μ

m.

4. A liquid crystal device comprising a semiconductor device according to claim 1.

5. A semiconductor device mounting structure, comprising:

a semiconductor device comprising

a first substrate having a first edge and a second edge substantially perpendicular to the first edge and also including a plurality of first electrodes and a plurality of second electrodes;

a second substrate including a plurality of electrode terminals;

a resin for bonding the first substrate and the second substrate together, wherein each of first and second electrodes is electrically connected to a corresponding one of the electrode terminals; and

a plurality of conductive particles in the resin;

wherein the plurality of first electrodes are aligned with the first edge, each of the first electrodes having a base surface formed on the first substrate, an upper surface, and a pair of opposing side walls aligned with the second edge, wherein, for each of the first electrodes, the cross-sectional width between the pair of opposing side walls linearly decreases from the upper surface towards the base surface;

wherein the plurality of second electrodes are aligned with the second edge, each of the second electrodes having a base surface formed on the first substrate, an upper surface, and a pair of opposing side walls aligned with the first edge, wherein, for each of the second electrodes, the cross-sectional width between the pair of opposing side walls linearly decreases from the upper surface towards the base surface; and

wherein the resin is able to flow outwardly through gaps between adjacent first electrodes and gaps between adjacent second electrodes when the first substrate and the second substrate are bonded together.

6. The semiconductor device mounting structure of claim 5, wherein the upper surface of each electrode faces a surface of the corresponding electrode terminal, each upper surface having a width of between about 15 μ

m and about 20 μ

m.

7. The semiconductor device mounting structure of claim 5, wherein the upper portions of adjacent first electrodes and the upper portions of adjacent second electrodes are separated from each other by a gap of between about 20 μ

m and about 25 μ

m.

8. A semiconductor device, comprising:

an IC having a first edge and a second edge substantially perpendicular to the first edge;

a substrate to which the IC is mounted;

a resin for bonding the IC and the substrate together;

a plurality of conductive particles in the resin;

a plurality of first electrodes aligned with the first edge, each of the first electrodes having a base surface formed on the IC, an upper surface, and a pair of opposing side walls aligned with the second edge, wherein, for each of the first electrodes, the cross-sectional width between the pair of opposing side walls linearly decreases from the upper surface towards the base surface; and

a plurality of second electrodes aligned with the second edge, each of the second electrodes having a base surface formed on the IC, an upper surface, and a pair of opposing side walls aligned with the first edge, wherein, for each of the second electrodes, the cross-sectional width between the pair of opposing side walls linearly decreases from the upper surface towards the base surface;

wherein the resin is able to flow outwardly through gaps between adjacent first electrodes and gaps between adjacent second electrodes when the IC and the substrate are bonded together.

9. A semiconductor device of claim 8, wherein the first and the second edges intersect to form a corner.

10. A liquid crystal device comprising a semiconductor device according to claim 8.

11. A semiconductor device, comprising:

a substrate;

an IC including a first edge and a second edge substantially perpendicular to the first edge, the IC being mounted on the substrate by heat-compressing;

a resin for joining the IC and the substrate;

a plurality of conductive particles in the resin;

a plurality of bumps aligned with the first edge, each of the bumps having a base surface formed on the IC, an upper surface, a pair of opposing side walls aligned with the second edge, wherein, for each of the bumps, the cross-sectional width between the pair of opposing side walls linearly decreases from the upper surface towards the base surface;

wherein the resin flows through gaps between adjacent bumps in the process of the heat-compressing.

12. A semiconductor device, comprising:

an IC including at least one edge;

a substrate to which the IC is mounted by heat-compressing;

a resin for joining the IC and the substrate;

a plurality of conductive particles in the resin;

a plurality of bumps aligned with the at least one edge, each of the bumps having an upper surface and a pair of opposing side walls; and

a plurality of spaces formed between each of two adjacent bumps, each space between two adjacent bumps linearly increasing in width from top to bottom;

wherein the resin flows through the spaces between adjacent electrodes during the process of heat-compressing.

13. A semiconductor device comprising a substrate, an IC having a first edge and a second edge substantially perpendicular to the first edge, a resin for joining the IC and the substrate, a plurality of conductive particles in the resin, a plurality of bumps aligned with the first edge, each of the bumps having a base surface formed on the IC, an upper surface, a pair of opposing side walls aligned with the second edge, wherein, for each of the bumps, the cross-sectional width between the pair of opposing side walls linearly decreases from the upper surface towards the base surface, the semiconductor device manufactured by a process comprising the steps of:

depositing the resin on the substrate;

arranging the IC on the substrate; and

pressing the substrate and IC together;

wherein the resin flows through gaps between adjacent bumps during the pressing step.