Ball grid array chip packages having improved testing and stacking characteristics

• US 6,448,664 B1
• Filed: 11/13/2001
• Issued: 09/10/2002
• Est. Priority Date: 05/16/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tay, Wuu Yean, Fook, Jeffrey Toh Tuck
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Lee, Kyung S.
• Application Number:
  US10/011,196
• Time in Patent Office: 301 Days
• Field of Search: 257/780, 257/672, 257/673, 257/676, 257/692, 257/698, 257/737, 257/738, 257/787, 257/48, 438/17, 438/18, 438/613, 438/625
• US Class Current: 257/780
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: G01R 1/0483 Sockets for un-leaded IC's having matrix type contact fields, e.g. BGA or PGA devices; Sockets for unpackaged, naked chips for IC's with connecting points around the edges only G01R1/0433
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05K 1/181 : associated with surface mounted components
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low profile BGA or FBGA semiconductor package is needed. The stackable ball grid array (BGA) or fine ball grid array (FBGA) provides a semiconductor package that is capable of being burned in and tested in a more efficient and cost effective manner than prior known BGA or FBGA semiconductor packages. A high density, low profile memory module incorporating a plurality of the disclosed BGA or FBGA semiconductor packages in a stacked arrangement is further disclosed.

Claims

1. A memory module assembly comprising:

a module board having a first surface and a second surface including, the module board having at least one electrical circuit to be placed in electrical contact with at least one ball grid array semiconductor package;

at least one of the first and the second surfaces of the module board comprising;

at least one first ball grid array semiconductor package attached to the at least one of the first and the second surfaces of the module board by a plurality of mutually complementary connective elements in electrical communication with the at least one electrical circuit of the module board, the at least one first ball grid array semiconductor package comprising;

a substrate having a first surface, a second surface, and an aperture extending from the first surface through the substrate to the second surface, a plurality of substrate bond pads located on the first surface proximate to the aperture;

the plurality of connective elements in electrical communication with the module board being attached to and extending from the second surface of the substrate being arranged in a preselected grid array pattern having at least one preselected pitch dimension between adjacent connective elements;

a semiconductor device having an active surface and a plurality of bond pads thereon, the semiconductor device attached to the second surface of the substrate and positioned adjacent the module board;

a plurality of bond wires extending through the aperture, each of the plurality of bond wires connecting one of the plurality of bond pads on the active surface of the semiconductor device with one of the plurality of substrate bond pads on the first surface of the substrate; and

the substrate including a plurality of mutually discrete electrically conductive circuit traces, each circuit trace of the plurality of circuit traces selectively extending from one of the plurality of substrate bond pads to one of the plurality of connective elements.

2. The memory module assembly of claim 1, further comprising:

at least one second ball grid array semiconductor package having a substrate having at least one electrical circuit;

the at least one second ball grid array semiconductor package stacked onto and mechanically and electrically attached to the at least one first ball grid array semiconductor package by a second plurality of mutually complementary connective elements extending from the first surface of the substrate of the at least one first ball grid array semiconductor package to the substrate of the at least one second ball grid array semiconductor package; and

the second plurality of mutually complementary connective elements being arranged in a preselected grid array pattern and at least one of the second plurality of connective elements being in contact with the at least one electrical circuit of the substrate of the at least one second ball grid array semiconductor package.

3. The memory module assembly of claim 2, further comprising:

at least one additional first ball grid array semiconductor package attached to the remaining opposite surface of the module board in which the at least one first ball grid array semiconductor package is attached;

the at least one additional first ball grid array semiconductor package mechanically and electrically attached to the opposite surface of the module board by a third plurality of mutually complementary connective elements extending between the opposite surface of the module board and the substrate of the at least one additional first ball grid array semiconductor package; and

the third plurality of connective elements being in electrical communication with the at least one electrical circuit of the module board.

4. The memory module assembly of claim 3, further comprising:

at least one additional second ball grid array semiconductor package having a substrate having at least one electrical circuit;

the at least one additional second ball grid array semiconductor package stacked onto and mechanically and electrically attached to the at least one additional first ball grid array semiconductor package by a fourth plurality of mutually complementary connective elements extending from the first surface of the substrate of the at least one additional first ball grid array semiconductor package to the substrate of the at least one additional second ball grid array semiconductor package; and

the fourth plurality of mutually complementary connective elements being arranged in a preselected grid array pattern and at least one of the fourth plurality of connective elements being in contact with the at least one electrical circuit of the substrate of the at least one additional second ball grid array semiconductor package.

5. The memory module assembly of claim 4, wherein at least one of the pluralities of mutually complementary connective elements comprises a solder ball.

6. The memory module assembly of claim 5, wherein at least one of the pluralities of mutually complementary connective elements further comprises a solder ball contact pad.

7. The memory module assembly of claim 6, wherein at least one of the pluralities of mutually complementary connective elements further comprises two solder ball contact pads, each of said solder ball contact pads accommodating the solder ball therebetween.

8. The memory module assembly of claim 7, wherein at least one of the solder ball contact pads comprises a concave-shaped surface for accommodating the solder ball.

9. A method of constructing a memory module comprising:

providing a module board having a first surface and a second surface, the module board having at least one electrical circuit adapted to accommodate connective elements of at least one ball grid array semiconductor package;

providing at least one first ball grid array semiconductor package having a substrate of a preselected cross-sectional thickness having a first surface, a second surface, and an aperture extending from the first surface through the substrate to the second surface, a plurality of substrate bond pads located on the first surface proximate to the aperture;

providing a plurality of contact elements located on the second surface of the substrate, each of the plurality of contact elements extending an approximate preselected distance from the second surface and being arranged in a preselected grid array pattern having at least one preselected pitch dimension between adjacent contact elements of the plurality of contact elements;

providing a semiconductor device having an active surface and a plurality of bond pads thereon, the semiconductor device attached to the second surface of the substrate, the semiconductor device extending a preselected distance from the second surface of the substrate;

providing a plurality of bond wires extending through the aperture, each of the plurality of bond wires connecting one of the plurality of bond pads on the active surface of the semiconductor device with one of the plurality of substrate bond pads on the first surface of the substrate;

providing the substrate with a plurality of mutually discrete electrically conductive circuit traces, each circuit trace of the plurality of circuit traces selectively extending from one of the plurality of substrate bond pads to one of the plurality of contact elements;

positioning the at least one first ball grid array semiconductor package proximately adjacent to at least one of the first and the second surfaces of the module board; and

attaching the connective elements of the at least one ball grid array semiconductor package to the module board and placing the connective elements in electrical communication with the at least one electrical circuit of the module board.

10. The method of constructing the memory module of claim 9, wherein providing the plurality of contact elements of the at least one first ball grid array semiconductor package comprises a contact pad and a solder ball and the attaching and the placing of the connective elements comprises mechanically and electrically attaching the solder ball of each connective element to a respective contact pad provided on at least one of the first and the second surfaces of the module board.

11. The method of constructing the memory module of claim 9, further comprising providing the at least one first ball grid array semiconductor package with a plurality of contact pads on the first surface of the substrate arranged in a preselected pattern to accommodate a second ball grid array semiconductor package.

12. The method of constructing the memory module of claim 11, further comprising:

providing the second ball grid array semiconductor package comprising a substrate having connective elements on a surface thereof arranged in a pattern complementary to the plurality of contact pads of the first surface of the substrate of the at least one first ball grid array semiconductor package; and

mechanically and electrically attaching the connective elements of the second ball grid array semiconductor package to the respective plurality of contact pads provided on the first surface of the at least one first ball grid array semiconductor package.

13. The method of constructing the memory module of claim 12, wherein providing the second ball grid array semiconductor package comprises attaching a second semiconductor device to the same surface of the substrate of the second ball grid array semiconductor package as the connective elements of the second ball grid array semiconductor package.

14. The method of constructing the memory module of claim 13, wherein providing the second ball grid array semiconductor package comprises providing at least one of the connective elements with a contact pad having a concave surface accommodating a solder ball.

15. The method of constructing the memory module of claim 13, further comprising:

providing and electrically and mechanically attaching to the remaining surface of the module board at least one third ball grid array semiconductor package by way of a plurality of connective elements extending from a surface of a substrate of the at least one third ball grid array semiconductor package; and

providing and electrically and mechanically attaching a fourth ball grid array semiconductor package to the at least one third ball grid array semiconductor package by way of a plurality of connective elements extending from a surface of a substrate of the fourth ball grid array semiconductor package.

16. The method of constructing the memory module of claim 15, wherein providing and electrically and mechanically attaching the at least one third and the fourth ball grid array semiconductor packages further comprises providing at least one of the plurality of connective elements of the at least one third and the fourth ball grid array semiconductor packages with at least one contact pad accommodating a solder ball.

17. The method of constructing the memory module of claim 16, wherein providing at least one of the plurality of connective elements of the at least one third and fourth ball grid array semiconductor packages further comprises providing the at least one contact pad with a concave surface for accommodating the solder ball.

18. The method of constructing the memory module of claim 15, wherein providing and electrically and mechanically attaching the at least one third ball grid array semiconductor package comprises attaching a semiconductor device to the same surface of the substrate as the plurality of connective elements extend from the at least one third ball grid array semiconductor package to the remaining surface of the module board.

19. The method of constructing the memory module of claim 15, wherein providing and electrically and mechanically attaching the fourth ball grid array semiconductor package comprises attaching a semiconductor device to the same surface of the substrate as the plurality of connective elements extend from the fourth ball grid array semiconductor package to the at least one third ball grid array semiconductor package.

20. The method of constructing the memory module of claim 9, wherein providing the at least one first ball grid array semiconductor package further comprises:

burning-in and testing the semiconductor device of the at least one ball grid array semiconductor package prior to attaching the connective elements of the at least one first ball grid array semiconductor package to the module board by electrically contacting at least one of a plurality of test pads provided on the substrate of the at least one first ball grid array semiconductor package.

21. The method of constructing the memory module of claim 20, wherein burning-in and the testing of the semiconductor device of the at least one ball grid array semiconductor package further comprises disassociating the plurality of test pads provided on the substrate of the at least one first ball grid array semiconductor package prior to attaching the connective elements of the at least one first ball grid array semiconductor package to the module board.

22. The method of constructing the memory module of claim 15, wherein providing the at least one first, the second, the at least one third, and the fourth ball grid array semiconductor packages further comprises:

burning-in and testing the semiconductor device of the at least one of the provided ball grid array semiconductor packages by electrically contacting at least one of a plurality of test pads provided and arranged in a preselected pattern on the substrate of the at least one provided ball grid array semiconductor packages prior to attaching the at least one of the provided semiconductor packages to the module board or to one of the other ball grid array semiconductor packages.

23. The method of constructing the memory module of claim 22, wherein burning-in and testing the semiconductor device of the at least one of the provided ball grid array semiconductor packages by electrically contacting the at least one of the plurality of test pads provided on the substrate of the at least one provided ball grid array semiconductor packages further comprises disassociating the plurality of test pads from the substrate of the at least one of the provided ball grid array semiconductor packages prior to attaching the at least one of the provided semiconductor packages to the module board or to one of the other ball grid array semiconductor packages.

24. The method of constructing the memory module of claim 22, wherein burning-in and testing the semiconductor device of the at least one of the provided ball grid array semiconductor packages further comprises arranging the plurality of test pads to correspond to a thin small outline package pin-out pattern.