High current and high accuracy linear amplifier

• US 6,448,748 B1
• Filed: 03/01/2001
• Issued: 09/10/2002
• Est. Priority Date: 03/01/2001
• Status: Expired due to Term

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Taylor, Michael F., Lim, Teck-Shiun
• Primary Examiner(s): Berhane, Adolf Deneke
• Application Number:
  US09/797,511
• Publication Number:
  US 20020121885A1
• Time in Patent Office: 558 Days
• Field of Search: 323/274, 323/276, 323/280, 323/281, 323/282
• US Class Current: 323/280
• CPC Class Codes: G05F 1/461 using an operational amplifier as final control device
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2203/30057 the SEPP power transistors are realised as paralleled FETs, i.e. the push or the pull transistor
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 3/303 using opamps as driving stages
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit

Abstract

A high-accuracy linear amplifier is disclosed for sinking or sourcing current to or from a load. The linear amplifier includes input circuitry for receiving a predetermined input signal and rectifier circuitry. The rectifier circuitry is disposed at the output of the input circuitry and is operative in response to the input signal to generate a source/sink command signal. Output stage circuitry is coupled to the rectifier circuitry and includes a current sink transistor and a current source transistor. The output stage circuitry is responsive to the command signal to sink or source current through one of the respective transistors. The amplifier further includes feedback circuitry coupled between the output of the output stage circuitry and the input circuitry to provide an error signal for modifying the input signal. Bias circuitry maintains the non-conducting transistor in an on state during the sourcing or sinking of current.

Claims

1. A high-accuracy linear amplifier for sinking or sourcing current to or from a load, said linear amplifier including:

input circuitry for receiving a predetermined input signal;

rectifier circuitry disposed at the output of said input circuitry and operative in response to said input signal to generate a source/sink command signal;

output stage circuitry coupled to said rectifier circuitry and including a current sink transistor and a current source transistor, said output stage circuitry responsive to said command signal to sink or source current through one of said respective transistors;

feedback circuitry coupled between the output of said output stage circuitry and said input circuitry to provide an error signal for modifying said input signal; and

bias circuitry to maintain the non-conducting transistor in an on state during the sourcing or sinking of current.

2. A high-accuracy linear amplifier according to claim 1 and further including:

high-speed boost circuitry coupled between said output stage output and said rectifier input.

3. A high-accuracy linear amplifier according to claim 1 wherein said rectifier circuitry includes:

a current source path including said current source transistor;

a current sink path including said current sink transistor; and

op amp circuitry coupled to said paths to establish a common node between said transistors, said respective source and sink transistors operative in response to said command voltage to cause current flow through one of said paths depending on the polarity of said command signal.

4. A high-accuracy linear amplifier according to claim 3 wherein:

said current source and sink paths are disposed in series, and

said op amp circuitry comprises first and second op amps associated respectfully with said current source path and said current sink path.

5. A high-accuracy linear amplifier according to claim 3 wherein:

said current source and sink paths are disposed in parallel, and

said op amp circuitry comprises a first op amp coupled to both paths.

6. A high-accuracy linear amplifier according to claim 1 wherein said output stage circuitry includes:

respective source current and sink current paths, said paths including respective source and sink transistors disposed in a common-source configuration and respective source and sink impedances to generate a predetermined transconductance; and

respective source current and sink current op amps coupled to said respective source current and sink current transistors, each of said op amps responsive to a command signal to source or sink current through said source or sink transistors.

7. A high-accuracy linear amplifier according to claim 6 wherein:

each of said paths include a single FET in series with said impedance.

8. A high-accuracy linear amplifier according to claim 6 wherein:

each of said paths include a plurality of FETs disposed in parallel, and collectively connected in series with said impedance.

9. A high-accuracy linear amplifier according to claim 1 wherein said bias circuitry includes:

a voltage rail;

a set resistor coupled to said voltage rail;

a current source disposed in series with said set resistor to establish a fixed voltage drop across said set resistor;

a sense resistor disposed between said voltage rail and said FET source terminal; and

an op amp having a positive input coupled to said fixed voltage drop, a negative input coupled in a feedback path to said FET source terminal and an output coupled to said FET gate terminal, said op amp operative to control the voltage across said sense resistor,

whereby the bias current generated in said FET is independent of drive current, load current and FET heating.

10. A DUT power supply for use with automatic test equipment, said DUT power supply including:

a digital controller;

a switching DC-DC converter; and

a linear amplifier, said linear amplifier including input circuitry for receiving a predetermined input signal;

rectifier circuitry disposed at the output of said input circuitry and operative in response to said input signal to generate a source/sink command signal;

output stage circuitry coupled to said rectifier circuitry and including a current sink transistor and a current source transistor, said output stage circuitry responsive to said command signal to sink or source current through one of said respective transistors;

feedback circuitry coupled between the output of said output stage circuitry and said input circuitry to provide an error signal for modifying said input signal; and

bias circuitry to maintain the non-conducting transistor in an on state during the sourcing or sinking of current.

11. A DUT power supply according to claim 10 and further including:

a load board coupled to said digital controller and said linear amplifier.

12. A DUT power supply according to claim 10 wherein said linear amplifier further includes:

high-speed boost circuitry coupled between said output stage output and said rectifier input.

13. A bias circuit for maintaining a linear amplifier output stage in an on state, said power supply output stage including an FET with respective gate, drain, and source terminals and configured as a common-source amplifier, said bias circuit including:

a voltage rail;

a set resistor coupled to said voltage rail;

a current source disposed in series with said set resistor to establish a fixed voltage drop across said set resistor;

a sense resistor disposed between said voltage rail and said FET source terminal; and

an op amp having a positive input coupled to said fixed voltage drop, a negative input coupled in a feedback path to said FET source terminal and an output coupled to said FET gate terminal, said op amp operative to cooperate with said current source to control the voltage across said sense resistor,

whereby the bias current generated in said FET is independent of drive current, load current and FET heating.

14. A rectifier circuit for directing a command voltage to source or sink current to or from respective source or sink FET output stage transistors, said rectifier circuit including:

a current source path including a current source transistor;

a current sink path including a current sink transistor; and

op amp circuitry coupled to said paths to establish a common node between said transistors, said respective source and sink transistors operative in response to said command voltage to cause current flow through one of said paths depending on the polarity of said command signal.

15. A rectifier circuit according to claim 14 wherein:

said current source and sink paths are disposed in series, and

said op amp circuitry comprises first and second op amps associated respectfully with said current source path and said current sink path.

16. A rectifier circuit according to claim 14 wherein:

said current source and sink paths are disposed in parallel, and

said op amp circuitry comprises a first op amp coupled to both paths.

17. A modular output stage for use in a linear amplifier, said modular output stage including:

respective source current and sink current paths, said paths including respective source and sink transistors disposed in a common-source configuration and respective source and sink impedances to generate a predetermined transconductance; and

respective source current and sink current op amps coupled to said respective source current and sink current transistors, each of said op amps responsive to a command signal to source or sink current through said source or sink transistors.

18. A modular output stage according to claim 17 wherein:

each of said paths include a single FET in series with said impedance.

19. A modular output stage according to claim 17 wherein:

each of said paths include a plurality of FETs disposed in parallel, and collectively connected in series with said impedance.

20. An indirect current monitor circuit for indicating changes in current output from a device-under-test power supply, said power supply having respective positive and negative voltage rails, at least one output stage, and bias circuitry for biasing said output stage, said indirect current monitor circuit including:

a first instrumentation amplifier coupled to said positive bias circuitry;

a second instrumentation amplifier coupled to said negative bias circuitry; and

a summing amplifier having an input coupled to the outputs of said first and second instrumentation amplifiers for detecting changes in current in said positive and negative bias circuits,

whereby said changes in current in said bias circuits represent changes in current from said at least one output stage.