Three-phase pulse width modulation waveform generator
First Claim
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1. A three-phase pulse width modulation waveform generator having at least an up-down counting circuitry which comprises:
- an up-down counter for performing an up-count or a down-count upon an external input of a count clock signal; and
a count controller having an output side connected to an input side of said up-down counter for sending said input side of said up-down counter a count enable signal which enables said up-down counter to perform said up-count or said down-count;
wherein said count controller has an input side which is connected to said up-down counter for receiving a count direction switching signal from said up-down counter, so that said count controller changes a cycle for generating said count enable signal in accordance with said count direction switching signal; and
wherein said input side of said count controller receives said count clock and counts said count clock, so that if a counted value of said count clock by said count controller is made to correspond to a predetermined value stored in said count controller, then said count controller generates said count enable signal.
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Abstract
The present invention provides a three-phase pulse width modulation waveform generator having at least an up-down counting circuitry which comprises: an up-down counter for performing an up-count or a down-count upon an external input of a count clock signal; and a count controller having an output side connected to an input side of the up-down counter for sending the input side of the up-down counter a count enable signal which enables the up-down counter to perform the up-count or the down-count.
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Citations
12 Claims
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1. A three-phase pulse width modulation waveform generator having at least an up-down counting circuitry which comprises:
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an up-down counter for performing an up-count or a down-count upon an external input of a count clock signal; and
a count controller having an output side connected to an input side of said up-down counter for sending said input side of said up-down counter a count enable signal which enables said up-down counter to perform said up-count or said down-count;
wherein said count controller has an input side which is connected to said up-down counter for receiving a count direction switching signal from said up-down counter, so that said count controller changes a cycle for generating said count enable signal in accordance with said count direction switching signal; and
wherein said input side of said count controller receives said count clock and counts said count clock, so that if a counted value of said count clock by said count controller is made to correspond to a predetermined value stored in said count controller, then said count controller generates said count enable signal. - View Dependent Claims (2, 3, 4, 5, 6)
a clock counter receiving said count clock and counting said count clock; and
a counting register for storing a registered counting value; and
a comparator being connected to said counting register for receiving said registered counting value from said counting register, said comparator being also connected to said clock counter for receiving a counted value from said clock counter, said comparator being also connected to said up-down counter, and said comparator comparing said counted value to said registered counting value and transmitting a count enable signal to said up-down counter when said counted value corresponds to said registered counting value.
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4. The three-phase pulse width modulation waveform generator as claimed in claim 3, wherein said count controller further comprises:
an AND-logic gate having a first input terminal receiving a count direction switching monitoring signal externally inputted and a second input terminal connected to an output terminal of said comparator for receiving said count enable signal from said comparator, said AND-logic gate performing an AND-operation of a value of said count direction switching monitoring signal and a value of said count enable signal to generate a count renewal enable signal, and said AND-logic gate having an output terminal connected to said counting register for transmitting said value of said count direction switching monitoring signal to said counted register.
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5. The three-phase pulse width modulation waveform generator as claimed in claim 4, wherein said count controller further more comprises:
a buffer register connected to said counting register for allowing a central processing unit to re-write a counting value and for transmitting a counting value to said counting register at the same time when said AND-logic gate generates said count renewal enable signal.
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6. The three-phase pulse width modulation waveform generator as claimed in claim 2, wherein said count controller comprises:
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a buffer register connected to said counting register for allowing a central processing unit to re-write a counting value stored in said buffer register;
a down-counter connected to said buffer register for receiving said counting value from said buffer register, said down-counter also receiving a count clock for counting said count clock, and said down-counter generating a count enable signal; and
an AND-logic gate having a first input terminal receiving a count direction switching monitoring signal externally inputted and a second input terminal connected to an output terminal of said down-counter for receiving said count enable signal from said down-counter, said AND-logic gate performing an AND-operation of a value of said count direction switching monitoring signal and a value of said count enable signal to generate a load enable signal, and said AND-logic gate having an output terminal connected to said down-counter for transmitting said load enable signal to said down-counter.
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7. An up-down counting circuitry in a pulse width modulation waveform generator circuit, said up-down counting circuitry comprising:
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an up-down counter for performing an up-count or a down-count upon an external input of a count clock signal; and
a count controller having an output side connected to an input side of said up-down counter for sending said input side of said up-down counter a count enable signal which enables said up-down counter to perform said up-count or said down-count;
wherein said count controller has an input side which is connected to said up-down counter for receiving a count direction switching signal from said up-down counter, so that said count controller changes a cycle for generating said count enable signal in accordance with said count direction switching signal; and
wherein said input side of said count controller receives said count clock and counts said count clock, so that if a counted value of said count clock by said count controller is made to correspond to a predetermined value stored in said count controller, then said count controller generates said count enable signal. - View Dependent Claims (8, 9, 10, 11, 12)
a clock counter receiving said count clock and counting said count clock; and
a counting register for storing a registered counting value; and
a comparator being connected to said counting register for receiving said registered counting value from said counting register, said comparator being also connected to said clock counter for receiving a counted value from, said clock counter, said comparator being also connected to said up-down counter, and said comparator comparing said counted value to said registered counting value and transmitting a count enable signal to said up-down counter when said counted value corresponds to said registered counting value.
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10. The up-down counting circuitry as claimed in claim 9, wherein said count controller further comprises:
an AND-logic gate having a first input terminal receiving a count direction switching monitoring signal externally inputted and a second input terminal connected to an output terminal of said comparator for receiving said count enable signal from said comparator, said AND-logic gate performing an AND-operation of a value of said count direction switching monitoring signal and a value of said count enable signal to generate a count renewal enable signal, and said AND-logic gate having an output terminal connected to said counting register for transmitting said value of said count direction switching monitoring signal to said counted register.
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11. The up-down counting circuitry as claimed in claim 10, wherein said count controller further more comprises:
a buffer register connected to said counting register for allowing a central processing unit to re-write a counting value and for transmitting a counting value to said counting register at the same time when said AND-logic gate generates said count renewal enable signal.
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12. The up-down counting circuitry as claimed in claim 8, wherein said count controller comprises:
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a buffer register connected to said counting register for allowing a central processing unit to re-write a counting value stored in said buffer register;
a down-counter connected to said buffer register for receiving said counting value from said buffer register, said down-counter also receiving a count clock for counting said count clock, and said down-counter generating a count enable signal; and
an AND-logic gate having a first input terminal receiving a count direction switching monitoring signal externally inputted and a second input terminal connected to an output terminal of said down-counter for receiving said count enable signal from said down-counter, said AND-logic gate performing an AND-operation of a value of said count direction switching monitoring signal and a value of said count enable signal to generate a load enable signal, and said AND-logic gate having an output terminal connected to said down-counter for transmitting said load enable signal to said down-counter.
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Specification