Circuits and methods for linearizing capacitor calibration and systems using the same
First Claim
1. A method of linear capacitor calibration in a switched capacitor circuit including first and second arrays of capacitors and at least one trim capacitor, each capacitor having a first plate coupled to a node, comprising the steps of:
- coupling second plates of each of the capacitors of the first array and the trim capacitor to a selected one of first and second reference voltages to present a corresponding impedance at the node;
sampling the corresponding first and second reference voltages on to the capacitors of the first array and the trim capacitors with a switch coupled to the node, the switch injecting an amount of charge on the node;
coupling second plates of each capacitor of the second array to a selected one of the first and second voltages to compensate for a voltage offset caused by the injected charge; and
recoupling the second plate of the trim capacitor to a selected one of the first and second voltages to calibrate a corresponding capacitor the first array.
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Accused Products
Abstract
A switched capacitor circuit includes a plurality of capacitor arrays coupled to a node, including an input array, a trim array associated with a selected capacitor of the input array and an offset compensation array. A first plurality of switches selectively couple capacitors of the input and trim arrays to selected reference voltages to approximate an impedance presented at the node during a subsequent operation to trim the selected capacitor of the input array. A sampling switch samples the selected reference voltages onto the input and trim arrays, the sampling switch injecting a corresponding amount of charge on the node. A second plurality of switches then selectively couples capacitors of the offset compensation array to the selected reference voltages to compensate for the amount of charge injected onto the node.
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Citations
20 Claims
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1. A method of linear capacitor calibration in a switched capacitor circuit including first and second arrays of capacitors and at least one trim capacitor, each capacitor having a first plate coupled to a node, comprising the steps of:
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coupling second plates of each of the capacitors of the first array and the trim capacitor to a selected one of first and second reference voltages to present a corresponding impedance at the node;
sampling the corresponding first and second reference voltages on to the capacitors of the first array and the trim capacitors with a switch coupled to the node, the switch injecting an amount of charge on the node;
coupling second plates of each capacitor of the second array to a selected one of the first and second voltages to compensate for a voltage offset caused by the injected charge; and
recoupling the second plate of the trim capacitor to a selected one of the first and second voltages to calibrate a corresponding capacitor the first array. - View Dependent Claims (2, 3, 4, 5, 6, 7)
coupling the second plate of a selected capacitor of the first array to the first reference voltage; and
coupling the second plate of the trim capacitor and the selected one of the capacitors being calibrated to the second reference voltage.
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3. The method of claim 1 wherein the first reference voltage is a positive reference voltage and the second reference voltage is ground.
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4. The method of claim 1 wherein the first reference voltage is ground and the second reference voltage is a positive reference voltage.
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5. The method of claim 1 wherein said step of sampling comprises the step of coupling the node to a common mode voltage.
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6. The method of claim 1 wherein said step of selectively coupling the second plates of the capacitors of the second array comprises the substep of performing a bit-cycling routine through the capacitors of the second array.
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7. The method of claim 1 wherein the trim capacitor comprises one of a plurality of capacitors in a trim array and said step of recoupling comprises the substep of performing a bit cycling operation through the capacitors of the trim array.
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8. A charge redistribution analog to digital converter comprising:
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a comparator for comparing voltages presented at first and, second comparator inputs;
an input capacitor array coupled to the first comparator input;
an offset compensation capacitor array coupled to the first comparator input;
a trim capacitor array coupled to the first comparator input; and
switching circuitry for;
during an offset compensation sampling phase;
coupling a selected capacitor of the input array to a first reference voltage and a selected capacitor of the input array being calibrated to a second reference voltage;
coupling selected capacitors of the trim array to the second reference voltage; and
sampling the first and second reference voltages onto the selected capacitors of the input and trim capacitor arrays, the switching circuitry causing a voltage offset at the first input of the comparator;
during an offset compensation conversion phase bit cycling through the capacitors of the offset compensation array to compensate for the voltage offset; and
during a calibration phase, bit cycling through capacitors of the trim array to calibrate the selected capacitor of the input array being calibrated. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A switched-capacitor circuit comprising:
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a plurality of capacitor arrays coupled to a node including an input array, a trim array associated with a selected capacitor of the input array and an offset compensation array;
a first plurality of switches for selectively coupling capacitors of the input and trim arrays to selected reference voltages to approximate an impedance presented at the node during a subsequent operation to trim the selected capacitor of the input array;
a sampling switch for sampling the selected reference voltages onto the input and trim arrays, the sampling switch injecting a corresponding amount of charge on the node; and
a second plurality of switches for selectively coupling capacitors of the offset compensation array to the selected reference voltages to compensate for the amount of charge injected on the node. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification