Circuits and methods for linearizing capacitor calibration and systems using the same

• US 6,448,911 B1
• Filed: 07/30/2001
• Issued: 09/10/2002
• Est. Priority Date: 07/30/2001
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Somayajula, Shyam S
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): NGUYEN, JOHN B
• Application Number:
  US09/918,852
• Time in Patent Office: 407 Days
• Field of Search: 341/155, 341/156, 341/172, 341/118, 341/144, 341/161, 341/150, 341/120, 341/121, 340/347
• US Class Current: 341/120
• CPC Class Codes: H03M 1/1019 by storing a corrected or correction value in a digital look-up table
• CPC Class Codes: H03M 1/1061 using digitally programmable trimming circuits
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array

Abstract

A switched capacitor circuit includes a plurality of capacitor arrays coupled to a node, including an input array, a trim array associated with a selected capacitor of the input array and an offset compensation array. A first plurality of switches selectively couple capacitors of the input and trim arrays to selected reference voltages to approximate an impedance presented at the node during a subsequent operation to trim the selected capacitor of the input array. A sampling switch samples the selected reference voltages onto the input and trim arrays, the sampling switch injecting a corresponding amount of charge on the node. A second plurality of switches then selectively couples capacitors of the offset compensation array to the selected reference voltages to compensate for the amount of charge injected onto the node.

Claims

1. A method of linear capacitor calibration in a switched capacitor circuit including first and second arrays of capacitors and at least one trim capacitor, each capacitor having a first plate coupled to a node, comprising the steps of:

coupling second plates of each of the capacitors of the first array and the trim capacitor to a selected one of first and second reference voltages to present a corresponding impedance at the node;

sampling the corresponding first and second reference voltages on to the capacitors of the first array and the trim capacitors with a switch coupled to the node, the switch injecting an amount of charge on the node;

coupling second plates of each capacitor of the second array to a selected one of the first and second voltages to compensate for a voltage offset caused by the injected charge; and

recoupling the second plate of the trim capacitor to a selected one of the first and second voltages to calibrate a corresponding capacitor the first array.

2. The method of claim 1 wherein said step of selectively coupling the second plates of the capacitors of the first array and the trim capacitor to a selected one of first and second reference voltages comprises the substeps of:

coupling the second plate of a selected capacitor of the first array to the first reference voltage; and

coupling the second plate of the trim capacitor and the selected one of the capacitors being calibrated to the second reference voltage.

3. The method of claim 1 wherein the first reference voltage is a positive reference voltage and the second reference voltage is ground.

4. The method of claim 1 wherein the first reference voltage is ground and the second reference voltage is a positive reference voltage.

5. The method of claim 1 wherein said step of sampling comprises the step of coupling the node to a common mode voltage.

6. The method of claim 1 wherein said step of selectively coupling the second plates of the capacitors of the second array comprises the substep of performing a bit-cycling routine through the capacitors of the second array.

7. The method of claim 1 wherein the trim capacitor comprises one of a plurality of capacitors in a trim array and said step of recoupling comprises the substep of performing a bit cycling operation through the capacitors of the trim array.

8. A charge redistribution analog to digital converter comprising:

a comparator for comparing voltages presented at first and, second comparator inputs;

an input capacitor array coupled to the first comparator input;

an offset compensation capacitor array coupled to the first comparator input;

a trim capacitor array coupled to the first comparator input; and

switching circuitry for;

during an offset compensation sampling phase;

coupling a selected capacitor of the input array to a first reference voltage and a selected capacitor of the input array being calibrated to a second reference voltage;

coupling selected capacitors of the trim array to the second reference voltage; and

sampling the first and second reference voltages onto the selected capacitors of the input and trim capacitor arrays, the switching circuitry causing a voltage offset at the first input of the comparator;

during an offset compensation conversion phase bit cycling through the capacitors of the offset compensation array to compensate for the voltage offset; and

during a calibration phase, bit cycling through capacitors of the trim array to calibrate the selected capacitor of the input array being calibrated.

9. The analog to digital converter of claim 8 wherein the trim array is a selected one of a plurality of trim arrays, each trim array associated with a capacitor in the input array.

10. The analog to digital converter of claim 8 wherein the first comparator input is a positive input and the first reference voltage is a positive reference voltage and the second voltage is ground.

11. The analog to digital converter of claim 8 wherein the first comparator input is a negative input and the first reference voltage is ground and the second reference voltage is a positive reference voltage.

12. The analog to digital converter of claim 9 wherein the trim array comprises a plurality of capacitors of a number selected as a function of a bit being represented by the capacitor of the input array being calibrated and a desired calibration resolution.

13. The analog to digital converter of claim 8 wherein the offset compensation capacitor array is a selected one of a plurality of offset compensation capacitor arrays coupled in parallel to the first comparator input.

14. The analog to digital converter of claim 8 wherein the analog to digital converter is a selected one of a plurality of like interleaved analog to digital converters.

15. A switched-capacitor circuit comprising:

a plurality of capacitor arrays coupled to a node including an input array, a trim array associated with a selected capacitor of the input array and an offset compensation array;

a first plurality of switches for selectively coupling capacitors of the input and trim arrays to selected reference voltages to approximate an impedance presented at the node during a subsequent operation to trim the selected capacitor of the input array;

a sampling switch for sampling the selected reference voltages onto the input and trim arrays, the sampling switch injecting a corresponding amount of charge on the node; and

a second plurality of switches for selectively coupling capacitors of the offset compensation array to the selected reference voltages to compensate for the amount of charge injected on the node.

16. The switched capacitor circuit of claim 15 and further comprising a third plurality of switches for selectively coupling capacitors of the trim array to the selected reference voltages to trim the associated selected capacitor of the input array.

17. The switched capacitor circuit of claim 15 wherein the node is coupled to an input of a comparator circuit.

18. The switched capacitor circuit of claim 15 wherein the first and second plurality of switches are controlled by a successive approximation return path.

19. The switched capacitor circuit of claim 15 wherein the plurality of capacitor arrays form a portion of a charge-redistribution analog to digital converter.

20. The switched capacitor circuit of claim 15 wherein the selected reference voltages are selected from the group comprising a positive reference voltage and ground.