RGB self-alignment and intelligent clock recovery

• US 6,449,017 B1
• Filed: 12/04/1998
• Issued: 09/10/2002
• Est. Priority Date: 12/04/1998
• Status: Expired due to Fees

• Current Assignee: Ching-Chyi Thomas Chen
• Original Assignee: Ching-Chyi Thomas Chen
• Inventors: Chen, Ching-Chyi Thomas
• Primary Examiner(s): LEE, MICHAEL
• Application Number:
  US09/205,438
• Time in Patent Office: 1,376 Days
• Field of Search: H04/N.512, 348/536, 348/537, 348/538, 348/539, 348/540, 348/541, 348/542, 348/543, 348/510, 348/512, 348/513, 348/514, 348/516
• US Class Current: 348/539
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H04N 9/44 Colour synchronisation

Abstract

A clock-recovery system is used to align a clock-phase with the RGB-signals. A frequency-synthesizing loop is applied for receiving a reference clock signal (CKREF) to generate a synthesized frequency. A fine-tuned frequency-synthesizing loop then receives a horizontal synchronization signal (HSYNC) to fine-tune the synthesized frequency into a fine-tuned synthesized frequency. A phase divider subdivides the fine-tuned synthesized frequency into a multiple phase segments for inputting to a multiplex controller. An analog sensor, receives and senses the RGB signals for generating encoded sensing data corresponding to voltage transitions of the RGB signals. A transition detector then applies the encoded sensing data for generating transition-detection data. A threshold triggering circuit compares the transition-detection data with a threshold data and triggering a RGB-phase data upon detecting the threshold data is exceeded by the transition detection data. A phase sampling detector applies the RGB-phase data for selecting a clock-alignment phase-segment from one of the multiple phase segments received from the multiplex controller for aligning the clock-phase. A digital phase-lock loop (PLL) includes a phase shift-direction detector (PD) receives the RGB-phase data from the threshold triggering circuit and the clock-alignment phase-segment from the multiplex controller for generating a dynamic phase-shift difference. The digital PLL further includes a digital filter to receive the dynamic phase-shift difference from the PD for generating a phase-segment-shift signal for outputting to the multiplex controller for shifting the clock-alignment phase-segment to dynamically align the clock-phase.

Claims

1. A clock recovery system for aligning a clock-phase with RGB signals comprising:

a frequency synthesizing loop for receiving a reference clock signal (CKREF) to generate a synthesized frequency;

a fine-tuned frequency synthesizing loop for receiving a horizontal synchronization signal (HSYNC) to fine tune said synthesized frequency into a fine-tuned synthesized frequency;

a phase divider for subdividing said fine-tuned synthesized frequency into a multiple phase segments for inputting to said multiplex controller;

a multiplex controller for receiving said multiple phase-segments subdivided;

an analog sensor for receiving and sensing said RGB signals for generating encoded sensing data corresponding to voltage transitions of said RGB signals;

a transition detection means for applying said encoded sensing data for generating transition-detection data;

a threshold triggering circuit for comparing said transition-detection data with a threshold data and triggering a RGB-phase data upon detecting said threshold data is exceeded by said transition detection data;

a phase sampling means for applying said RGB-phase data for selecting a clock-alignment phase-segment from one of said multiple phase segments received from said multiplex controller for aligning said clock-phase;

a digital phase-lock loop (PLL) includes a phase shift-direction detector (PD) for receiving said RGB-phase data from said threshold triggering circuit and said clock-alignment phase-segment from said multiplex controller for generating a dynamic phase-shift difference; and

said digital PLL further includes a digital filter for receiving said dynamic phase-shift difference from said digital PD for generating a phase-segment-shift signal for outputting to said multiplex controller for shifting said clock-alignment phase-segment to dynamically align said clock-phase.

2. The clock recovery system of claim 1 further comprising:

a manual on-screen adjustment (OSD) means provided for user selection of said clock-alignment phase segment for inputting to said multiplex controller.

3. The clock recovery system of claim 1 further comprising:

a latch circuit receiving said clock-alignment phase-segment from said multiplex controller for aligning and latching a clock of an A/D converter to said clock-alignment phase-segment.

4. A clock recovery system for aligning a clock-phase with RGB signals comprising:

an analog sensor for receiving and sensing said RGB signals for generating encoded sensing data corresponding to voltage transitions of said RGB signals;

a transition detection means for applying said encoded sensing data for generating transition-detection data;

a threshold triggering circuit for comparing said transition-detection data with a threshold data and triggering a RGB-phase data upon detecting said threshold data is exceeded by said transition detection data;

a multiplex controller for receiving a multiple phase-segments subdivided from a clock frequency cycle; and

a phase sampling means for applying said RGB-phase data for selecting a clock-alignment phase-segment from one of said multiple phase segments received from said multiplex controller for aligning said clock-phase.

5. The clock recovery system of claim 4 further comprising:

a fine-tuned frequency synthesizing loop for receiving a horizontal synchronization signal (HSYNC) to synthesized a fine-tuned synthesized frequency; and

a phase divider for subdividing said fine-tuned synthesized frequency into said multiple phase segments for inputting to said multiplex controller.

6. The clock recovery system of claim 5 further comprising:

a phase-lock loop (PLL) includes a phase shift-direction detector (PD) for receiving said RGB-phase data from said threshold triggering circuit and said clock-alignment phase-segment from said multiplex controller for generating a dynamic phase-shift difference; and

said digital PLL further includes a digital filter for receiving said dynamic phase-shift difference from said PD for generating a phase-segment-shift signal for outputting to said multiplex controller for shifting said clock-alignment phase-segment to dynamically align said clock-phase.

7. The clock recovery system of claim 4 further comprising:

a frequency synthesizing loop for receiving a reference clock signal (CKREF) to generate a synthesized frequency; and

a phase divider for subdividing said synthesized frequency into said multiple phase segments for inputting to said multiplex controller.

8. A clock recovery system for aligning a clock-phase with RGB signals comprising:

a voltage transition detector for detecting voltage transitions from said RGB signals; and

a phase sampling means for applying said voltage transitions for determining an optimal phase segment for aligning said clock-phase with said RGB signals.

9. The clock recovery system of claim 8 further comprising:

a digital phase-lock loop (PLL) includes a phase shift-direction detector (PD) for receiving said voltage transitions from said voltage transition detector and said optimal phase segment from said phase sampling means for generating a dynamic phase-shift difference for shifting said optimal phase segment for dynamically aligning said clock-phase with said RGB signals.

10. A method of processing red-green-blue (RGB) analog signals for converting said RGB analog signals to corresponding digital signals for image display comprising:

a) receiving a reference clock (CKREF) signal as a digital signal;

b) generating a synthesized frequency (f2) by applying a phase-locking operation for locking a phase of said synthesized frequency with said reference clock (CKREF) signal;

c) dividing said synthesized A/D frequency (f2) into N-equal phase-segments where N is a positive integer; and

d) providing a static phase adjusting means to allow a user to align said synthesized frequency (f2) to align with an on-screen adjustment (OSD) user-selected phase segment among said N-equal phase-segments.

11. The method of claim 10 further comprising:

e) receiving horizontal synchronization (HSYNC) signals as digital signals and generating a fine-tuned synthesized frequency (f2′

) by performing a phase locking operation to lock a phase of said fine tuned synthesized frequency with said HSYNC signals;

e′

) dividing said fine-tuned synthesized frequency (f2′

) into N′

-equal phase-segments where N′

is a positive integer; and

f′

) providing a static phase adjusting means to allow a user to align said fine-tuned synthesized frequency (f2′

) to align with an on-screen adjustment (OSD) user-selected phase segment among said N′

-equal phase-segments.

12. The method of claim 10 further comprising:

d″

) dividing said synthesized frequency (f2) into N-equal phase-segments where N is a positive integer; and

f′

) detecting at least two voltage transitions from receiving a series of said RGB analog signals and generating a clock-phase select signal for automatically selecting an auto-selected phase-segment among said N-equal phase-segments for align said synthesized frequency (f2) to said phase-segment.

13. The method of claim 11 further comprising:

d″

′

) dividing said fine-tuned synthesized frequency (f2′

) into N′

-equal phase-segments where N′

is a positive integer; and

f″

) detecting at least two voltage transitions from receiving a series of said RGB analog signals and generating a clock-phase select signal for automatically selecting an auto-selected phase-segment among said N′

-equal phase-segments for align said fine-tuned synthesized frequency (f2′

) to said phase-segment.

14. The method of claim 12 further comprising:

g) periodically detecting voltage transitions from receiving a series of said RGB analog signals after a predefined elapsed-time and generating a dynamic clock-phase select signal for periodically selecting an auto-selected phase-segment among said N-equal phase-segments for align said synthesized frequency (f2) to said phase-segment.

15. The method of claim 13 further comprising:

g′

) periodically detecting voltage transitions from receiving a series of said RGB analog signals after a predefined elapsed-time and generating a dynamic clock-phase select signal for periodically selecting an auto-selected phase-segment among said N-equal phase-segments for align said N′

-equal phase-segments for align said fine-tuned synthesized frequency (f2′

) to said phase-segment.

16. A method for aligning a phase of a clock with RGB signals comprising:

a) receiving said RGB signals and detecting voltage transitions of said RGB signals; and

b) performing a phase sampling by applying said voltage transitions and aligning said phase of said clock with said RGB signals.

17. The method for aligning a cock-phase with RGB signals of claim 16 further comprising a step of:

a1) receiving an HSYNC data for determining a frequency for said clock.