Ferroelectric memory system and method of driving the same

• US 6,449,183 B1
• Filed: 11/22/2000
• Issued: 09/10/2002
• Est. Priority Date: 06/27/1997
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Corporation (Panasonic Holdings Corporation)
• Inventors: Hirano, Hiroshige, Takeo, Masato
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/717,254
• Time in Patent Office: 657 Days
• Field of Search: 365/145, 365/149, 365/189.09, 365/211
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

Under application of a voltage V3 to a cell plate line PC, a voltage difference appearing on a bit line BL and an inverted bit line /BL in accordance with a polarized state of a memory cell capacitor and a line capacitance is amplified by a sense amplifier, thereby reading data. A read time for this read operation is tR, which is substantially the same as a write time tWL of L data and a write time tWH of H data. Also, the same voltage is used in a write operation and a read operation. Specifically, the operations are conducted with a write energy larger than a read energy. As a result, a read error can be avoided. Furthermore, since an energy not saturating polarization of a ferroelectric film is used in a write operation, there is no need to provide a voltage increasing circuit, and a high operation can be realized.

Claims

1. A ferroelectric memory system comprising:

a bit line;

a cell plate line;

a ferroelectric capacitor including a ferroelectric film and disposed between said bit line and said cell plate line;

a memory cell transistor disposed between said bit line and said ferroelectric capacitor; and

a writing control circuit for supplying a first energy for polarizing said ferroelectric film of said ferroelectric capacitor between said cell plate line and said bit line,

wherein said writing control circuit controls said first energy in a manner that said ferroelectric film is placed in substantially the same polarized state against a temperature change and said writing control circuit controls to conduct a write operation at a higher voltage when a temperature is lower.

2. The ferroelectric memory system of claim 1, further comprising reading control means for supplying a second energy for reading a polarized state of said ferroelectric film,

wherein said second energy is smaller than said first energy.

3. The ferroelectric memory system of claim 1 or 2,

wherein said writing control circuit supplies a write signal with a larger pulse width as a temperature is lower.

4. The ferroelectric memory system of claim 3,

wherein said writing control circuit includes:

an internal voltage generation circuit for generating an internal voltage signal that has a lower voltage as a temperature is lower; and

a circuit for receiving said internal voltage signal generated by said internal pulse signal generation circuit and generating a pulse signal having a larger pulse width as the voltage of said internal voltage signal is lower.

5. A ferroelectric memory system comprising:

a first bit line;

a first ferroelectric capacitor which is connected with the first bit line via a first memory cell transistor and between the first bit line and a cell plate line to form a memory cell; and

a write circuit for conducting, with a first energy, the operation of writing data in the first ferroelectric capacitor in a desired polarization direction, the ferroelectric memory system characterized in that,

the write circuit is a circuit designed such that the first energy retains a substantially constant state against temperature change, and

the write circuit is a circuit that at a first temperature, conducts the write operation at a first voltages and at a second temperature lower than the first temperature, conducts the write operation at a second voltage higher than the first voltage.

6. The ferroelectric memory system of claim 5, further comprising a circuit having an operating mode of conducting, with a first energy, the operation of writing data in the first ferroelectric capacitor in a desired polarization direction and of conducting, with a second energy, the operation of reading polarization data written in the first ferroelectric capacitor, the first energy being greater than the second energy.

7. A ferroelectric memory system comprising:

a first bit line;

a first ferroelectric capacitor which is connected with the first bit line via a first memory cell transistor and between the first bit line and a cell plate line to form a memory cell; and

a write circuit for conducting, with a first energy, the operation of writing data in the first ferroelectric capacitor in a desired polarization direction, the ferroelectric memory system characterized in that,

the write circuit is a circuit designed such that the first energy retains a substantially constant state against temperature change, and

the write circuit is a circuit that at a first temperature, conducts the write operation with a first pulse width, and at a second temperature lower than the first temperature, conducts the write operation with a second pulse width larger than the first pulse width.

8. The ferroelectric memory system of claim 7, further comprising a circuit having an operating mode of conducting, with a first energy, the operation of writing data in the first ferroelectric capacitor in a desired polarization direction and of conducting, with a second energy, the operation of reading polarization data written in the first ferroelectric capacitor, the first energy being greater than the second energy.

9. The ferroelectric memory system of claim 8, wherein the write circuit is a circuit made up of an internal voltage generation circuit and a pulse signal generation circuit, in which the internal voltage generation circuit generates a internal voltage signal to generate a low voltage at a low temperature and the pulse signal generation circuit receives the internal voltage signal as a power source and generates a pulse signal.

10. The ferroelectric memory system of claim 7, wherein the write circuit is a circuit made up of an internal voltage generation circuit and a pulse signal generation circuit, in which the internal voltage generation circuit generates an internal voltage signal to generate a low voltage at a low temperature and a pulse signal generation circuit receives the internal voltage signal as a power source and generates a pulse signal.