Method and apparatus for coupling noise reduction in a semiconductor device

• US 6,449,195 B1
• Filed: 09/28/2000
• Issued: 09/10/2002
• Est. Priority Date: 09/28/2000
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Barrera, David D., Min, Don-Sun, Taufique, Md H
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US09/677,697
• Time in Patent Office: 712 Days
• Field of Search: 365/189.05, 365/154, 365/156, 365/63, 365/206
• US Class Current: 365/189.05
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

An integrated circuit is disclosed that includes a first signal line adjacent to a second signal line. A first latch is coupled between the first and second signal line. The first latch includes a first transistor having a first current electrode coupled to the first signal line and a control electrode coupled to the second control line and a second transistor having a first current electrode coupled to the second signal line and a control electrode coupled to the first signal line. The first signal line typically runs substantially parallel to the second signal line. A signal generator circuit may be coupled to a first end of the first and second signal lines and a receiver circuit may be coupled to a second end of the first and second signal line. The first latch may be coupled closer to the second end of the first and second signal lines than the first end of the first and second signal lines. In one embodiment, the signal generator circuit comprises a precharge circuit that precharges the first and second signal lines to a predetermined voltage such as a low state or a high state. The circuit may include additional signal lines and additional latches where a latch is coupled between each pair of adjacent signal lines. In an embodiment in which the latch transistors are NMOS transistors, the second current electrodes of each of the transistors is coupled to a ground node. The signal lines may comprise the word lines of a semiconductor memory.

Claims

1. An integrated circuit, comprising:

a first signal line adjacent to a second signal line;

a first latch coupled between the first and second signal line, wherein the first latch includes;

a first transistor having a first current electrode coupled to the first signal line and a control electrode coupled to the second control line, and

a second transistor having a first current electrode coupled to the second signal line and a control electrode coupled to the first signal line;

a third signal line adjacent to the second signal line; and

a second latch coupled between the second and third signal lines, wherein the second latch includes;

a third transistor having a first current electrode coupled to the second signal line and a control electrode coupled to the third signal line, and

a fourth transistor having a first current electrode coupled to the third signal line and a control electrode coupled to the second signal line.

2. The integrated circuit of claim 1, wherein the first signal line runs substantially parallel to the second signal line.

3. The integrated circuit of claim 1, further comprising a signal generator circuit coupled to a first end of the first, second, and third signal lines.

4. The integrated circuit of claim 3, further comprising a receiver circuit coupled to a second end of the first, second, and third signal lines, wherein the first latch and the second latch are coupled closer to the second end of the first, second, and third signal lines than the first end of the first, second, and third signal lines.

5. The integrated circuit of claim 3, wherein the signal generator circuit comprises a precharge circuit that precharges the first and second signal lines to a predetermined voltage.

6. The integrated circuit of claim 5, wherein the predetermined voltage is one of a low state and a high state.

7. The integrated circuit of claim 2, wherein the third signal line runs substantially parallel to the second signal line.

8. The integrated circuit of claim 1, wherein:

the first transistor has a second current electrode coupled to a voltage supply node;

the second transistor has a second current electrode coupled to the voltage supply node;

the third transistor has a second current electrode coupled to the voltage supply node; and

the fourth transistor has a second current electrode coupled to the voltage supply node.

9. The integrated circuit of claim 1, wherein each one of the first, second, third, and fourth transistors comprises one of an NMOS and a PMOS transistor.

10. The integrated circuit of claim 1, wherein the signal lines are of a type selected from a group consisting of word lines and row/column decoders.

11. An integrated circuit, comprising:

a word line driver circuit;

a first word line coupled to the word line driver circuit;

a second word line, adjacent to the first word line, coupled to the word line driver circuit;

a first latch coupled between the first and second word lines, wherein the first latch includes;

a first transistor having a first current electrode coupled to the first word line and a control electrode coupled to the second word line; and

a second transistor having a first current electrode coupled to the second word line and a control electrode coupled to the first word line.

12. The integrated circuit of claim 11, wherein:

the first transistor has a second current electrode coupled to a voltage supply node; and

the second transistor has a second current electrode coupled to the voltage supply node.

13. The integrated circuit of claim 11, further comprising:

a third word line adjacent to the second word line;

a second latch coupled between the second and third word lines, wherein the second latch includes;

a third transistor having a first current electrode coupled to the second word line and a control electrode coupled to the third word line, and

a fourth transistor having a first current electrode coupled to the third word line and a control electrode coupled to the second word line.

14. The integrated circuit of claim 11, further comprising:

a first bitline and a second bitline, each coupled to the first and second word lines; and

a sense amplifier coupled to the first and second bitline.

15. An integrated circuit, comprising:

a first signal line adjacent to a second signal line;

a first latch coupled between the first and second signal line, the first latch reducing cross coupling noise upon a transition of the second signal line from a first state to a second state, wherein the first latch includes;

a first transistor having a first current electrode coupled to the first signal line and a control electrode coupled to the second control line, and

a second transistor having a first current electrode coupled to the second signal line and a control electrode coupled to the first signal line.

16. The integrated circuit of claim 15, wherein the first signal line runs substantially parallel to the second signal line.

17. The integrated circuit of claim 15, further comprising a signal generator circuit coupled to a first end of the first and second signal lines.

18. The integrated circuit of claim 17, further comprising a receiver circuit coupled to a second end of the first and second signal lines, wherein the first latch is coupled closer to the second end of the first and second signal lines than the first end of the first and second signal lines.

19. The integrated circuit of claim 17, wherein the signal generator circuit comprises a precharge circuit that precharges the first and second signal lines to a predetermined voltage.

20. The integrated circuit of claim 19, wherein the predetermined voltage is one of a low state and a high state.

21. The integrated circuit of claim 15, further comprising:

a third signal line adjacent to the second signal line;

a second latch coupled between the second and third signal lines, the second latch reducing cross coupling noise upon the transition of the second signal line from the first state to the second state, wherein the second latch includes;

a third transistor having a first current electrode coupled to the second signal line and a control electrode coupled to the third signal line, and

a fourth transistor having a first current electrode coupled to the third signal line and a control electrode coupled to the second signal line.

22. The integrated circuit of claim 21, wherein:

the first transistor has a second current electrode coupled to a voltage supply node;

the second transistor has a second current electrode coupled to the voltage supply node;

the third transistor has a second current electrode coupled to the voltage supply node; and

the fourth transistor has a second current electrode coupled to the voltage supply node.

23. The integrated circuit of claim 15, wherein:

the first transistor has a second current electrode coupled to a voltage supply node; and

the second transistor has a second current electrode coupled to the voltage supply node.