Apparatus and method for programmable datapath arithmetic arrays

• US 6,449,628 B1
• Filed: 05/05/2000
• Issued: 09/10/2002
• Est. Priority Date: 05/07/1999
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: MorphICs Technology, Inc. (Infineon Technologies AG)
• Inventors: Wasson, Stephen L.
• Primary Examiner(s): NGO, CHUONG D
• Application Number:
  US09/565,649
• Time in Patent Office: 858 Days
• Field of Search: 708/230, 708/232, 708/234, 708/235, 708/236, 716/16, 326/37, 326/38, 326/39, 326/41
• US Class Current: 708/230
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A programmable data arithmetic array includes a set of data buses and a matrix of data arithmetic units including fixed function units and programmable function units connected to the set of data buses. Bidirectional interconnect is positioned between the set of data buses and the matrix of data arithmetic units.

Claims

1. A datapath arithmetic array, comprising:

a plurality of data buses;

a plurality of fixed function bit slice blocks coupled to said plurality of data buses and grouped into at least one fixed function datapath structure;

a plurality of re-programmable function bit slice blocks coupled to said plurality of data buses and grouped into at least one re-programmable function datapath structure; and

at least one control line in each datapath structure that is coupled to all bit slice blocks within the datapath structure.

2. The programmable datapath arithmetic array of claim 1, wherein each fixed function bit slice block is configured to perform one of a plurality of predetermined functions.

3. The programmable datapath arithmetic array of claim 2, wherein said predetermined functions include storage and arithmetic functions.

4. The datapath arithmetic array of claim 1, wherein at least two of said plurality of datapath structures are coupled via at least one of said plurality of data buses to form a datapath slice in said array.

5. The datapath arithmetic array of claim 4, wherein multiple datapath slices in said array are optionally coupled by one or more control lines.

6. The datapath arithmetic array of claim 1 further comprising:

a plurality of control lines coupled to each bit slice block in a datapath structure, wherein each of said plurality of control lines is not capable of being decoupled from any bit slice block within said datapath structure to which it is coupled.

7. The datapath arithmetic array of claim 6 wherein at least one bit slice block in a datapath structure is coupled to an adjacent bit slice block in an adjacent datapath structure.

8. The datapath arithmetic array of claim 1 wherein:

at least one fixed function bit slice block is coupled to a first quantity of operand lines and a second quantity of control lines; and

said fixed function bit slice block implements less than 2**N functions, where N is a sum of said first quantity of operand lines and said second quantity of control lines.

9. The datapath arithmetic array of claim 1 wherein:

at least one re-programmable function bit slice block is coupled to a first quantity of operand lines and a second quantity of control lines; and

said re-programmable bit slice block implements 2**N functions, where N is a sum of said first quantity of operand lines and said second quantity of control lines.