Method and apparatus for busing data elements

• US 6,449,671 B1
• Filed: 06/09/1999
• Issued: 09/10/2002
• Est. Priority Date: 06/09/1999
• Status: Expired due to Fees

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Patkar, Niteen A., Purcell, Stephen C., Van Dyke, Korbin S., Thusoo, Shalesh
• Primary Examiner(s): Dharia, Rupal
• Application Number:
  US09/328,971
• Time in Patent Office: 1,189 Days
• Field of Search: 710/100, 710/309, 710/310, 710/112, 710/52, 710/107, 711/141, 711/144, 711/105, 711/150, 711/146, 711/121, 711/143, 711/145
• US Class Current: 710/107
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems

Abstract

A method and apparatus for busing data elements within a computing system includes processing that begins by providing, on a shared bus, a first control signal relating to a first transaction during a first bus cycle. The processing continues by providing a second control signal relating to a second transaction and a first address signal relating to the first transaction during a second bus cycle. The processing continues by providing a third control signal relating to a third transaction and a second address signal relating to a second transaction during a third bus cycle. The processing then continues by providing a first status relating to the first transaction and a third addressing signal relating to the third transaction during a fourth bus cycle. The processing then continues by providing a second status relating to the second transaction during a fifth bus cycle. The processing then continues by providing first data relating to the first transaction when the first status is a hit and providing third status relating to the third transaction during a sixth bus cycle.

Claims

1. A method for busing data elements, the method comprises the steps of:

a) providing, on a shared bus, first control signaling relating to a first transaction in a first bus cycle;

b) providing, on the shared bus, second control signaling relating to a second transaction and first address signaling relating to the first transaction in a second bus cycle;

c) providing, on the shared bus, third control signaling relating to a third transaction and second address signaling relating to the second transaction in a third bus cycle, and determining by at least one processor coupled to the shared bus whether cache associated with the at least one processor includes data identified by the first address signaling;

d) providing, on the shared bus, first status relating to the first transaction and third address signaling relating to the third transaction in a fourth bus cycle;

e) providing, on the shared bus, second status relating to the second transaction in a fifth bus cycle and reading by the at least one processor the data from the cache when the at least one processor determined that the cache includes the data;

f) providing, on the shared bus, first data relating to the first transaction when the first status is a hit; and

g) providing, on the shared bus, third status relating to the third transaction in the sixth bus cycle.

2. The method of claim 1, wherein the first, second, and third control signaling corresponds to bus arbitration.

3. The method of claim 1, wherein the status comprises at least one of a hit indicator, a miss indicator, and a retry indicator.

4. The method of claim 1 further comprises, during a seventh bus cycle, writing, by a requesting processor, the data into cache associated with the requesting processor, wherein the requesting processor is associated with the first transaction.

5. The method of claim 3 further comprises, when the status includes the miss indicator:

splitting the first transaction, such that the data is retrieved from external memory during a subsequent bus cycle; and

utilizing bus cycles between the sixth bus cycle and the subsequent bus cycle for busing a data element of at least one other transaction.

6. The method of claim 3 further comprises, when the status is the retry indicator, re-providing the first control signaling relating to the first transaction in a bus cycle subsequent to the fourth bus cycle.

7. A method for busing data elements, the method comprises the steps of:

a) providing, for a first transaction on a shared bus, control signaling, address signaling, status, and data on a shared bus during a set of bus cycles, wherein the control signaling, the address signaling, the status, and the data have, with respect to each other, a fixed latency; and

b) providing, for a second transaction on the shared bus, second control signaling, second address signaling, second status, and second data on the shared bus during a second set of bus cycles, wherein the second control signaling, the second address signaling, the second status, and the second data have, with respect to each other, the fixed latency, wherein the second set of bus cycles overlaps the set of bus cycles such that the first and second transactions are provided on the shared bus in a pipelined manner, wherein the status comprise at least one of a hit indicator, a miss indicator, and a retry indicator; and

when the status is the retry indicator, re-providing the first control signaling relating to the first transaction in a bus cycle subsequent to interpreting of the status.

8. The method of claim 7, wherein the first transaction further comprises a fixed number of wait cycles for reading tags associated with the first transaction, a fixed number of wait cycles for reading data from a cache location, and a fixed number of wait cycles for writing the data to another cache location.

9. The method of claim 7, wherein, for the first transaction, the address signaling occurs in a first predetermined number of bus cycles after the control signaling, the status occurs in a second predetermined number of bus cycles after the address signaling, and the data occurs in a third predetermined number of bus cycles after the status.

10. The method of claim 7, wherein the each of the first, second, and third predetermined number of bus cycles includes one to four bus cycles.

11. The method of claim 7 further comprises, providing data relating to the first transaction when the status for the first transaction includes a hit indicator.

12. The method of claim 7 further comprises, when the status for the first transaction includes the miss indicator:

splitting the first transaction, such that the data is retrieved from external memory during a subsequent bus cycle; and

utilizing bus cycles after the status has been interpreted and the subsequent bus cycle for busing a data element of at least one other transaction.

13. A bus manager comprises:

a shared bus;

a processing module; and

memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to(a) enable providing of, on the shared bus, first control signaling-relating to a first transaction in a first bus cycle;

(b) enable providing of, on the shared bus, second control signaling relating to a second transaction and first address signaling relating to the first transaction in a second bus cycle;

(c) enable providing of, on the shared bus, third control signaling relating to a third transaction and second address signaling relating to the second transaction and determine whether cache includes data identified by the first address signaling in a third bus cycle;

(d) enable providing of, on the shared bus, first status relating to the first transaction and third address signaling relating to the third transaction in a fourth bus cycle;

(e) enable providing of, on the shared bus, second status relating to the second transaction and reading of data from the cache in a fifth bus cycle;

(f) enable providing of, on the shared bus, first data relating to the first transaction when the first status is a hit; and

(g) enable providing of, on the shared bus, third status relating to the third transaction in the sixth bus cycle.

14. The bus manager of claim 13, wherein the first, second, and third control signaling corresponds to bus arbitration.

15. The bus manager of claim 13, wherein the status comprises at least one of a hit indicator, a miss indicator, and a retry indicator.

16. The bus manager of claim 13, wherein the memory further comprises operational instructions that cause the processing module to, during a seventh bus cycle, write the data into another cache associated with the first transaction.

17. The bus manager of claim 15, wherein the memory further comprises operational instructions that cause the processing module to, when the status includes the miss indicator:

split the first transaction, such that the data is retrieved from external memory during a subsequent bus cycle; and

utilize bus cycles between the sixth bus cycle and the subsequent bus cycle for busing a data element of at least one other transaction.

18. The bus manager of claim 15, wherein the memory further comprises operational instructions that cause the processing module to, when the status is the retry indicator, re-provide the first control signaling relating to the first transaction in a bus cycle subsequent to the fourth bus cycle.

19. A bus manager comprises:

a shared bus;

a processing module; and

memory operably coupled to the processing module, wherein the memory stores operational instructions that cause the processing module to (a) provide, for a first transaction on the shared bus, control signaling, address signaling, status, and data on a shared bus during a set of bus cycles, wherein the control signaling, the address signaling, the status, and the data have, with respect to each other, a fixed latency; and

(b) provide, for a second transaction on the shared bus, second control signaling, second address signaling, second status, and second data on the shared bus during a second set of bus cycles, wherein the second control signaling, the second address signaling, the second status, and the second data have, with respect to each other, the fixed latency, wherein the second set of bus cycles overlaps the set of bus cycles such that the first and second transactions are provided on the shared bus in a pipelined manner, wherein the status comprises at least one of a hit indicator, a miss indicator, and a retry indicator, and when the status is the retry indicator, re-provide the first control signaling relating to the first transaction in a bus cycle subsequent to interpreting of the status.

20. The bus manger of claim 19, wherein the first transaction further comprises a fixed number of wait cycles for reading tags associated with the first transaction, a fixed number of wait cycles for reading data from a cache location, and a fixed number of wait cycles for writing the data to another cache location.

21. The bus manager of claim 19, wherein, for the first transaction, the address signaling occurs in a first predetermined number of bus cycles after the control signaling, the status occurs in a second predetermined number of bus cycles after the address signaling, and the data occurs in a third predetermined number of bus cycles after the status.

22. The bus manager of claim 19, wherein the each of the first, second, and third predetermined number of bus cycles includes one to four bus cycles.

23. The bus manager of claim 19, wherein the memory further comprises operational instructions that cause the processing module to, when the status for the first transaction includes the miss indicator:

split the first transaction, such that the data is retrieved from external memory during a subsequent bus cycle; and

utilize bus cycles after the status has been interpreted and the subsequent bus cycle for busing a data element of at least one other transaction.

24. The bus manager of claim 19, wherein the memory further comprises operational instructions that cause the processing module to, when the status is the hit indicator, provide data relating to the first transaction in a bus cycle subsequent to interpreting of the status.