Single platform electronic tester

• US 6,449,741 B1
• Filed: 10/30/1998
• Issued: 09/10/2002
• Est. Priority Date: 10/30/1998
• Status: Expired due to Term

• Current Assignee: Xcerra Corporation (COHU Incorporated)
• Original Assignee: LTX Corp. (COHU Incorporated)
• Inventors: Rosenfeld, Eric, Blethen, Roger W., Burlison, Phillip, Perkins, Jeffrey H., Kelly, H. Neil, Terrenzi, Edward J., Menis, David, Organ, Donald V., Hannaford, Christopher J., Berry, Tommie, Davis, Michael G., Curry, David W., Lanier, Kenneth J., Deome, Mark
• Primary Examiner(s): TU, CHRISTINE TRINH LE
• Application Number:
  US09/183,038
• Time in Patent Office: 1,411 Days
• Field of Search: 714/724, 714/725, 714/733, 714/734, 714/735, 714/736, 714/737, 714/738, 714/739, 714/25, 714/26, 714/30, 714/31, 714/32, 714/37, 714/44, 714/46, 714/47, 714/57, 324/763, 324/764, 324/758.1, 324/73.1, 324/537, 324/750
• US Class Current: 714/724
• CPC Class Codes: G01R 1/025 concerning dedicated user interfaces, e.g. GUI, or dedicated keyboards G01R31/31912 takes precedence
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/319 Tester hardware, i.e. output processing circuits

Abstract

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Claims

1. An electronic tester, comprising:

a test head to couple to a device under test, wherein the device under test can be system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit;

digital test circuitry that applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals;

analog test circuitry that applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals;

memory test circuitry that applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns;

a tester computer that supervises the application of digital, analog, and memory test signals from the digital test circuitry, analog test circuitry, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals, wherein the test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the tester computer are operable as a single platform, wherein the digital test signals, the analog test signals, and the memory test patterns can be applied serially or concurrently to the device under test.

2. The electronic tester of claim 1, wherein the memory test circuitry comprises an algorithmic pattern generator.

3. The electronic tester of claim 2, wherein the memory test circuitry further comprises a fail log memory.

4. The electronic tester of claim 1, wherein the digital test circuitry comprises a control pattern memory processing unit and a data pattern memory processing unit.

5. The electronic tester of claim 1, wherein the analog test circuitry comprises a sequenced measure system.

6. The electronic tester of claim 5, wherein the analog test circuitry further comprises vector radio frequency circuitry.

7. The electronic tester of claim 1, wherein the analog test circuitry comprises a pulsed power source.

8. The electronic tester of claim 1, wherein the digital test circuitry, the analog test circuitry, and the memory test circuitry are modular and reconfigurable.

9. An electronic tester, comprising:

means for applying digital test signals to a device under test and receiving digital outputs from the device under test in response to the digital test signals;

means for applying analog test signals to the device under test and receiving analog outputs from the device under test in response to the analog test signals;

means for applying memory test patterns to the device under test and receiving memory outputs from the device under test in response to the memory test patterns;

computing means for supervising the application of digital, analog, and memory test signals to the device under test by the means for applying digital test signals, analog test signals, and memory test patterns, wherein the device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, an analog integrated circuit, or a memory integrated circuit, wherein the means for applying digital test signals, the means for applying analog test signals, the means for applying memory test patterns, and the computing means are coupled to a single platform, wherein the digital test signals, the analog test signals, and the memory test patterns can be applied serially or concurrently to the device under test.

10. An electronic tester, comprising:

analog test circuitry that applies analog test signals to a device under test coupled to a test head and receives analog outputs from the device under test in response to the analog test signals;

a tester controller that sends action packets to the analog test circuitry to select characteristics of analog tests to be performed by the analog test circuitry;

digital test circuitry that applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals;

memory test circuitry that applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns;

a computer coupled to the tester controller, the digital test circuitry, and the memory test circuitry, wherein the computer causes the tester controller to send action packets to the analog test circuitry to execute analog tests of the device under test, wherein the computer causes the digital test circuitry to execute digital tests of the device under test, and wherein the computer causes the memory test circuitry to execute memory tests with respect to the device under test, wherein the analog tests, the digital tests, and the memory tests can be applied serially or concurrently to the device under test.

11. A method for an electronic tester, comprising:

presenting to a user of the electronic tester a computer-generated graphical user interface for launching an operating system for the electronic tester, wherein the operating system can oversee selectable serial or concurrent execution of digital test programs, analog test programs, and memory test programs for testing a device under test coupled to the electronic tester;

launching the operating system in response to user input via the computer-generated graphical user interface.