System and method for product yield prediction

• US 6,449,749 B1
• Filed: 11/18/1999
• Issued: 09/10/2002
• Est. Priority Date: 11/18/1999
• Status: Expired due to Term

• Current Assignee: PDF Solutions
• Original Assignee: PDF Solutions
• Inventors: Stine, Brian E.
• Primary Examiner(s): Smith, Matthew S.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US09/442,699
• Time in Patent Office: 1,027 Days
• Field of Search: 700/121, 716/1, 716/4, 716/5
• US Class Current: 716/56
• CPC Class Codes: G05B 15/02 electric
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

Claims

1. A method for predicting a yield for integrated circuits comprising:

a) providing information for fabricating at least one type of characterization vehicle having at least one feature which is representative of at least one type of feature to be incorporated into a final integrated circuit product;

b) fabricating a characterization vehicle which embodies layout features representative of the product employing at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product;

c) providing a product layout;

d) extracting layout characteristics from the product layout, comprising;

1) listing all structures in the characterization vehicle;

2) classifying each structure into families such that all structures in each family form an experiment over a particular attribute; and

3) for each family, determining which attributes are to be extracted for the product layout; and

e) using the extracted layout characteristics in connection with a yield model to produce a yield prediction.

2. A method in accordance with claim 1 wherein the families include a family comprising nest structures for exploring basic defectivity over a selected number of line widths and spaces.

3. A method in accordance with claim 1 wherein the families include a family comprising snake and comb structures for exploring yield over a predetermined range of line widths and spaces.

4. A method in accordance with claim 3, wherein the predetermined range of line widths and spaces include relatively large line widths next to relatively small spaces and relatively large interline spaces next to relatively small line widths.

5. A method in accordance with claim 1 wherein the families include a family comprising Kelvin critical dimension and van der Pauw structures for exploring critical dimension variation across line density, width and spacing.

6. A method in accordance with claim 1 wherein the families include a family comprising border structures for exploring the effect of various optical proximity correction schemes on yield.

7. A method according to claim 1, further comprising determining and ranking yield loss mechanisms given characterization vehicle data and extracted layout attributes.

8. A method for predicting a yield for an integrated circuit comprising:

a) providing a characterization vehicle having structures representative of structures to be incorporated into a final integrated circuit product;

b) providing a product layout;

c) extracting attributes of the product layout, comprising;

classifying the structures in the characterization vehicle into families of structures,

wherein each family of structures corresponds to an experiment for a particular attribute of the product layout;

for each family of structures, determining which attributes are to be extracted from the product layout; and

d) using the extracted attributes in connection with a yield model to produce a yield prediction.

9. A method in accordance with claim 8 wherein the families of structures includes a family of structures comprising nest structures for exploring basic defectivity over a selected number of line widths and spaces.

10. A method in accordance with claim 8 wherein the families of structures include a family of structures comprising snake and comb structures for exploring yield over a predetermined range of line widths and spaces.

11. A method in accordance with claim 10 wherein the predetermined range of line widths and spaces include relatively large line widths next to relatively small spaces and relatively large interline spaces next to relatively small line widths.

12. A method in accordance with claim 8 wherein the families of structures include a family of structures comprising Kelvin critical dimension and van der Pauw structures for exploring critical dimension variation across line density, width and spacing.

13. A method in accordance with claim 8 wherein the families of structures include a family of structures comprising border structures for exploring the effect of various optical proximity correction schemes on yield.

14. A system for predicting yield of integrated circuits comprising:

a) a characterization vehicle having structures representative of features to be incorporated into a final integrated circuit product;

b) a product layout; and

c) an extraction engine configured to;

classify the structures in the characterization vehicle into families of structures,

wherein each family of structures corresponds to an experiment for an attribute of the product layout,

for each family of structures, determine which attributes are to be extracted from the product layout; and

produce a yield prediction using the extracted attributes in connection with a yield model.

15. A system in accordance with claim 14 wherein the structures in the characterization vehicle are selected from the family consisting of:

a) Kelvin metal critical dimension structure;

b) snake structure;

c) comb structure;

d) snake and comb structures;

e) nest defect size distribution structure;

f) van der Pauw structure;

g) optical proximity correction structure; and

h) scanning electron microscopy structures.

16. A system in accordance with claim 14 wherein the extraction engine is also used when designing a characterization vehicle.