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Design verification device, method and memory media for integrated circuits

  • US 6,449,750 B1
  • Filed: 01/14/2000
  • Issued: 09/10/2002
  • Est. Priority Date: 01/18/1999
  • Status: Expired due to Fees
First Claim
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1. A design verification device for a semiconductor integrated circuit, the device comprising:

  • a mechanism for identifying an altered portion according to a disagreed portion of a circuit description from input means for inputting the circuit description before an alteration and a circuit description after the alteration; and

    verification means including (i) means for determining portions of the circuit description, which correspond to an output of each of registers, an external input to the circuit description and an output from the circuit description, as key points, and (ii) means for cutting out a logic connected between each of the key points and a preceding key point, as a logic circuit group, said verification means being used for carrying out formal verification for the logic circuit group that can assure an agreement or equivalence of the key point in the circuit descriptions before and after the alteration, and for carrying out verification by utilizing an event-driven simulation for the logic circuit group that cannot assure an agreement or equivalence of the key point to the circuit descriptions before and the after the alteration.

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