Instruction signature and primary input and primary output extraction within an IEEE 1149.1 compliance checker

• US 6,449,755 B1
• Filed: 07/14/2000
• Issued: 09/10/2002
• Est. Priority Date: 10/30/1997
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Singh, Harbinder, Beausang, James
• Primary Examiner(s): Smith, Mathew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/616,388
• Time in Patent Office: 788 Days
• Field of Search: 716/1-21, 703/13-17, 703/24-28, 714/30, 714/32, 714/33, 714/39, 714/726-729, 714/732-734
• US Class Current: 716/106
• CPC Class Codes: G01R 31/318591 Tools

Abstract

A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device_ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found. To infer the SAMPLE instruction, instructions selecting the BSR are groups and those that do not exhibit the behavior of the SAMPLE instruction are eliminated. Primary inputs and primary outputs are then inferred. The following instructions are then inferred: INTEST, HIGHZ, CLAMP, IDCODE and RUNBIST. As each of the above elements of the IEEE 1149.1 design are located, they are used to update the BSDD and are also inherently verified for compliance by the present invention. Intolerable violations flag a non-compliant design.

Claims

1. A computer implemented method for determining instructions that are implemented within an integrated circuit design, said method comprising the steps of:

a) extracting, from said integrated circuit design, a set of frontier pins associated with decode circuitry that is coupled to an instruction register;

b) automatically determining a set of unique signatures on said frontier pins, each unique signature representing an implemented instruction, said step b) comprising the steps of;

b1) applying opcodes to said instruction register and observing said frontier pins;

b2) recording all opcodes that map to each respective unique signature on said frontier pins and repeating step b2) for all opcodes applied at step b1);

c) extracting, from said integrated circuit design, a test data register selected by each unique signature of said set of unique signatures; and

d) updating a design database with information obtained by steps b) and c).

2. A method as described in claim 1 wherein said step a) comprises the steps of:

determining said frontier pins using a portion of said instruction register if said decode circuitry is placed after said instruction register; and

determining said frontier pins using a bounded backward trace process and simulation if said decode circuitry is placed between shift cells and update cells of said instruction register.

3. A method as described in claim 1 wherein said step c) comprises the steps of:

applying a unique signature to a test access port (TAP) controller;

using an active element simulation, determining a set of sequential cells within said integrated circuit design that remain constant;

applying tokens to said set of sequential cells that remain constant and simulating a shift-DR state of said TAP controller; and

recording a set of shift cells as a test data register associated with said unique signature by starting from TDO and traversing backwards to TDI following a path indicated by said tokens.

4. A method as described in claim 1 further comprising the steps of:

inferring an INTEST instruction based on a signature of said set of unique signatures that, when applied to a test access port (TAP) controller, exhibits proper conditioning of primary inputs and primary outputs of each boundary scan register cell;

inferring a HIGHZ instruction based on a signature of said set of unique signatures that, when applied to said TAP controller, drives said primary outputs to a high impedance state;

inferring a CLAMP instruction based on a signature of said set of unique signatures that, when applied to said TAP controller, exhibits proper conditioning of said primary outputs of each bypass register cell;

inferring a IDCODE instruction of said set of unique signatures; and

inferring a RUNBIST instruction of said set of unique signatures.

5. A method as described in claim 1 wherein said instruction register has a predetermined bits size and said predetermined bit size is eight bits.

6. A method as described in claim 1 further comprising the steps of:

inferring a SAMPLE instruction from said set of unique signatures by including signatures in a set that select a boundary scan register and eliminating signatures from said set that do not otherwise exhibit a predefined SAMPLE behavior; and

characterizing primary inputs of output cells of a boundary scan register by the following steps;

applying said SAMPLE instruction to a test access port (TAP) controller;

tracing backward, from a shift cell of a boundary scan register cell, to an extreme most point, said extreme most point characterized in that a token placed thereon is captured by said shift cell during simulation; and

testing if a token placed at said extreme most point is also output over a known output point of said boundary scan register cell.

7. A computer system comprising a processor coupled to a bus and a memory unit coupled to said bus, wherein instructions stored in said memory unit, when executed by said processor, implement a method for determining instructions that are implemented within a netlist, said method comprising the steps of:

a) extracting, from said netlist, a set of frontier pins associated with decode circuitry that is coupled to an instruction register;

b) automatically determining a set of unique signatures on said frontier pins, each unique signature representing an implemented instruction, said step b) comprising the steps of;

b1) applying opcodes to said instruction register and observing said frontier pins;

b2) recording all opcodes that map to each respective unique signature on said frontier pins and repeating step b2) for all opcodes applied at step b1);

c) extracting, from said netlist, a test data register selected by each unique signature of said set of unique signatures; and

d) updating a design database with information obtained by steps b) and c).

8. A computer system as described in claim 7 wherein said step a) comprises the steps of:

determining said frontier pins using a portion of said instruction register if said decode circuitry is placed after said instruction register; and

determining said frontier pins using a bounded backward trace process and simulation if said decode circuitry is placed between shift cells and update cells of said instruction register.

9. A computer system as described in claim 7 wherein said step c) comprises the steps of:

applying a unique signature to a test access port (TAP) controller;

using an active element simulation, determining a set of sequential cells within said netlist that remain constant;

applying tokens to said set of sequential cells that remain constant and simulating a shift-DR state of said TAP controller; and

recording a set of shift cells as a test data register associated with said unique signature by starting from TDO and traversing backwards to TDI following a path indicated by said tokens.

10. A computer system as described in claim 7 wherein said method further comprises the steps of:

inferring an INTEST instruction based on a signature of said set of unique signatures that, when applied to a test access port (TAP) controller, exhibits proper conditioning of primary inputs and primary outputs of each boundary scan register cell;

inferring a HIGHZ instruction based on a signature of said set of unique signatures that, when applied to said TAP controller, drives said primary outputs to a high impedance state;

inferring a CLAMP instruction based on a signature of said set of unique signatures that, when applied to said TAP controller, exhibits proper conditioning of said primary outputs of each bypass register cell;

inferring a IDCODE instruction of said set of unique signatures; and

inferring a RUNBIST instruction of said set of unique signatures.

11. A computer system as described in claim 7 wherein said instruction register has a predetermined bits size and said predetermined bit size is eight bits.

12. A computer system as described in claim 7 wherein said method further comprises the steps of:

inferring a SAMPLE instruction from said set of unique signatures by including signatures in a set that select a boundary scan register and eliminating signatures from said set that do not otherwise exhibit a predefined SAMPLE behavior; and

characterizing primary inputs of output cells of a boundary scan register by the following steps;

applying said SAMPLE instruction to a test access port (TAP) controller;

tracing backward, from a shift cell of a boundary scan register cell, to an extreme most point, said extreme most point characterized in that a token placed thereon is captured by said shift cell during simulation; and

testing if a token placed at said extreme most point is also output over a known output point of said boundary scan register cell.