Maintaining correspondence between text and schematic representations of circuit elements in circuit synthesis
First Claim
1. A method for designing logic circuits comprising;
- compiling a test representation of a logic circuit;
optimizing said logic circuit;
graphically displaying at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit;
selecting a portion of said text representation;
constructing a correlation between said portion of text representation and a portion of a graphic representation after optimizing said logic circuit;
assigning a first identifier tag to said text representation of said logic circuit, assigning a second identifier tag to said graphic representation of said logic circuit, said second identifier tag being linked to said first identifier tag; and
displaying said portion of said graphic representation which corresponds to said portion of said text representation.
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Accused Products
Abstract
A method and apparatus that maintains the correspondence between a text representation of a circuit element and the corresponding schematic representation of the element after optimization of the circuit containing the element. In one example of a method of the invention, a circuit containing element is described in text representation. A first tag is assigned to the text representation. The text representation is synthesized to produce a first schematic representation of the circuit element. A second tag corresponding to the first tag is assigned to the first schematic representation of the circuit element. The circuit containing the circuit element is optimized to produce a second schematic representation of the circuit element. A third tag corresponding to the first tag is assigned to the second schematic representation. Other methods and apparatuses are described.
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Citations
31 Claims
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1. A method for designing logic circuits comprising;
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compiling a test representation of a logic circuit;
optimizing said logic circuit;
graphically displaying at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit;
selecting a portion of said text representation;
constructing a correlation between said portion of text representation and a portion of a graphic representation after optimizing said logic circuit;
assigning a first identifier tag to said text representation of said logic circuit, assigning a second identifier tag to said graphic representation of said logic circuit, said second identifier tag being linked to said first identifier tag; and
displaying said portion of said graphic representation which corresponds to said portion of said text representation. - View Dependent Claims (2, 3)
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4. A method for designing logic circuits comprising:
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describing a first circuit in text representation;
assigning a first identifier tag to at least a portion of said text representation;
synthesizing said text representation to produce a first schematic representation of said first circuit;
assigning a second tag corresponding to said first tag to at least a portion of said first schematic representation of said first circuit;
optimizing, through a Boolean relationship, said first circuit to produce a second schematic representation of said first circuit;
constructing a correlation between at least said portion of said text representation and said second schematic representation after optimizing said first circuit; and
assigning a third tag corresponding to said first tag to at least a portion of said second schematic representation, said third tag being linked to said first tag. - View Dependent Claims (5, 6, 7)
displaying said second schematic representation;
displaying said text representation; and
displaying in highlight a portion of said text representation and displaying in highlight a portion of said second schematic representation.
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8. A computer readable medium having stored thereon sequences of instruction which are executable by a digital processing system, and which, when executed by the digital processing system, cause the system to preform a method comprising:
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compiling a text representation of a logic circuit;
optimizing said logic circuit;
graphically displaying at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit;
selecting a portion of said text representation;
constructing a correlation between said portion of text representation and a portion of a graphic representation after optimizing said logic circuit;
assigning a first identifier tag to said portion of said text representation;
assigning a second identifier tag to said portion of said graphic representation, said second identifier tag being linked to said first identifier tag; and
displaying said portion of said graphic representation which corresponds to said portion of said representation. - View Dependent Claims (9, 10, 11)
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12. A computer system comprising:
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a bus;
a data storage device coupled to said bus; and
a processor coupled to said data storage device, said processor operable to receive instruction which, when executed by the processor, cause the processor to perform a method comprising;
complining a text representation of a logic circuit;
optimizing said logic circuit for a target integrated circuit architecture;
graphically displaying a circuit representation of said logic circuit after optimizing said logic circuit;
selecting a portion of said text representation;
constructing a correlation between said portion of text representation and a portion of a graphic representation after optimizing said logic circuit;
assigning a first identifier tag to said portion of said text representation;
assigning a second identifier tag to said portion of said graphic representation, said second identifier tag being linked to said first identifier tag, and displaying said portion of said graphic representation which corresponds to said portion of said text representation. - View Dependent Claims (13, 14, 15)
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16. A method for designing logic circuits, said method comprising:
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compiling a text representation of a logic circuit;
optimizing said logic circuit through a Boolean relationship;
graphically displaying a graphical schematic of at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit;
selecting a portion of said graphical schematic;
constructing a correlation between said portion of said text representation and said portion of said graphical schematic after optimizing said logic circuit;
assigning a first identifier tag to said portion of said text representation;
assigning a second identifier tag to said portion of said text graphical schematic, said second identifier tag being linked to said first identifier tag; and
displaying a portion of said text representation which corresponds to said portion of said graphical schematic. - View Dependent Claims (17, 18, 19)
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20. A computer readable medium having stored thereon a sequence of executable instructions which, when executed on a digital processing system, cause said system to preform a method comprising:
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compiling a text representation of a logic circuit;
optimizing said logic circuit through a Boolean relationship;
graphically displaying a graphical schematic of at least a portion of a circuit representation of said logic circuit after optimizing said logic circuit;
selecting a portion of said graphical schematic;
constructing a correlation between said portion of said text representation and said portion of said graphical schematic after optimizing said logic circuit;
assigning a first identifier tag to said portion of said text representation;
assigning a second identifier tag to said portion of said graphical schematic, said second identifier tag being linked to said first identifier tag; and
displaying a portion of said text representation which corresponds to said portion of said graphical schematic. - View Dependent Claims (21, 22, 23)
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24. A method for designing logic circuits, said method comprising:
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displaying at least a portion of a text representation of a logic circuit;
selecting a first portion of said at least a portion of said text representation;
constructing a correlation between at least said portion of said text representation and a portion of graphical schematic after optimizing said logic circuit;
assigning a first identifier tag to said portion of said text representation;
assigning a second identifier tag to said graphical schematic, said second identifier tag being linked tag said first identifier tag;
displaying, in response to said selecting, a first portion of said graphical schematic which had been derived from said text representation and them optimized through a Boolean relationship.
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25. A method for designing logic circuits, said method comprising:
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displaying at least a portion of a graphical schematic of a logic circuit, said graphical schematic having been derived from a text representation of said logic circuit and the optimized through a Boolean relationship;
selecting a first portion of said graphical schematic;
constructing a correlation between said portion of said graphical schematic and said text representation after optimizing said logic circuit;
assigning a first identifier tag to said portion of said graphical schematic;
assigning a second identifier tag to said text representation, said second identifier tag being linked to said first identifier tag;
displaying, in response to said selecting, a portion of said representation from which said first portion of said graphical schematic was derived. - View Dependent Claims (26, 27, 28)
selecting for display a portion of said graphical schematic which is in a critical path of said logic circuit.
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27. A method as in claim 26 wherein said selecting specifies a particular type of logic gate for display such that a filtered graphical schematic of only said particular type of logic gates is displayed.
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28. A method as in claim 26 wherein said selecting is performed by a user manipulating a cursor control device to select said portion.
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29. A computer readable medium having stored thereon executable computer program instructions which, when executed by a digital processing system, cause said system to perform a method for designing logic circuits, said method comprising:
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generating a first representation of a logic circuit;
performing an optimization of said logic circuit to create a second representation which represents a transformation of said first representation, said optimization being performed through a Boolean relationship;
assigning a first identifier tag to said first representation;
assigning a second identifier tag to said second representation, said second identifier tag being linked to said first identifier tag; and
correlating a first set of intermediate nodes in said first representation to a second set of intermediate nodes in said second representation, wherein said correlating creates a set of matched tags for said first and said sescond sets of intermediate nodes after performing said optimization of said logic circuit. - View Dependent Claims (30, 31)
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Specification