Semiconductor device and process for manufacturing and packaging a semiconductor device

• US 6,451,627 B1
• Filed: 09/07/1999
• Issued: 09/17/2002
• Est. Priority Date: 09/07/1999
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Coffman, Samuel L.
• Primary Examiner(s): Talbott, David L.
• Assistant Examiner(s): Chambliss, Alonzo
• Application Number:
  US09/391,879
• Time in Patent Office: 1,106 Days
• Field of Search: 438/110, 438/111, 438/112, 438/113, 438/114, 438/115, 438/118, 438/123, 438/124, 438/126, 438/612, 438/127, 438/691, 438/106, 438/121, 298/27, 298/41, 257/692, 257/693, 257/734, 257/784, 257/787
• US Class Current: 438/111
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/85439 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85455 Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49582 Metallic layers on lead frames
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.

Abstract

A process for manufacturing a semiconductor device (70) using selective plating and etching to form the packaging for such device. A flat sheet (20) of conductive material is selectively plated with a conductive etch resistant material to form a plurality of die attach areas (22) on one side (23) of the sheet (20) and to define die contact (24) and lead contact (26) areas on the opposite side (27) of the sheet. Mold locks (34) which also serve as interconnect bonding areas are selectively plated on the side (23) of the sheet in association with each of the die attach areas (22). Semiconductor die (40) are attached to each of the die attach areas (22) and bonded (42) to the tops of the mold locks (34). A unitary molded resin housing (50) is formed overlying all of the semiconductor device die (40). The underside (27) of the conductive sheet (20) is selectively etched using the plated etch resistant material (24), (26) as an etch mask to form isolated die contact areas (60) and lead contact areas (62). The unitary housing (50) can then be sawed to separate the plurality of the semiconductor device die into a plurality of individual device structures (70).

Claims

1. A process for manufacturing a semiconductor device comprising the steps of:

providing a sheet of conductive material having first and second surfaces and a thickness;

selectively applying an etch resistant material to the second surface of the sheet;

forming a mold lock extending upwardly from the first surface of the sheet wherein the mold lock does not form a recess within the first surface of the sheet;

attaching a semiconductor die to the first surface of the sheet;

forming an electrical connection from the semiconductor die to the mold lock;

providing an encapsulating resin overlying the first surface of the sheet to encapsulate the mold lock, semiconductor die and electrical connection; and

selectively etching through the thickness of the sheet from the second surface using the etch resistant material as an etch mask to expose the encapsulating resin.

2. The process of claim 1 wherein the step of providing the sheet of conductive material comprises providing a copper sheet.

3. The process of claim 1 wherein the step of forming the mold lock comprises the steps of:

forming a patterned plating mask on the first surface of the sheet of conductive material;

plating portions of the sheet of conductive material exposed through openings in the patterned plating mask with copper; and

removing the patterned plating mask.

4. The process of claim 1 wherein the step of selectively applying comprises the steps of:

applying a layer of photo-imageable resist to the second surface;

patterning the layer of photo-imageable resist to form openings therethrough exposing portions of the second surface; and

plating portions of the second surface exposed through the openings with layers of nickel and palladium.

5. The process of claim 1 wherein the step of selectively applying comprises the step of selectively plating the second surface with sequential layers of nickel and gold.

6. The process of claim 1 further comprising the step of applying a layer of conductive material to the first surface of the sheet to form a die attach area.

7. The process of claim 1 wherein the step of providing the conductive material comprises the step of providing a layer of molybdenum sandwiched between first and second layers of copper.

8. The process of claim 7 wherein the step of forming the mold lock includes selectively etching the first layer of copper to form a pedestal structure having a surface.

9. The process of claim 7 wherein the step of forming the mold lock includes using the layer of molydenum as an etch stop material.

10. The process of claim 7 further including the step of selectively plating the conductive material on the surface of a pedestal structure.

11. The process of claim 10 wherein the step of selectively plating includes plating a layer of nickel over the surface of the pedestal structure.

12. The process of claim 11 wherein the step of selectively plating further includes plating palladium over the layer of nickel.

13. The process of claim 10 wherein the step of selectively plating includes plating a layer of copper on the surface of the pedestal.

14. The process of claim 13 wherein the step of selectively plating includes plating another conductive material on the layer of copper plated on the pedestal structure.

15. The process of claim 1 wherein the step of selectively applying comprises the steps of:

applying a layer of photo-imageable resist to the first surface;

patterning the layer of photo-imageable resist to form openings therethrough exposing portions of the first surface; and

plating portions of the first surface exposed through the openings with layers of nickel and palladium.

16. The process of claim 1 wherein the step of selectively applying comprises the step of selectively plating the first surface with sequential layers of nickel and gold.

17. A process for manufacturing a plurality of semiconductor devices comprising the steps of:

providing a sheet of a first conductive material having first and second sides;

selectively plating the first side of the sheet with a second conductive material to form a plurality of die attach areas;

selectively plating the second side of the sheet with a third etch resistant conductive material to define a plurality of device lead contacts and a plurality of device die contacts, the device die contacts being defined in alignment with the die attach areas;

selectively plating the first side of the sheet with a fourth conductive material to form a plurality of mold locks in alignment with the plurality of device lead contacts;

attaching a semiconductor die to each of the plurality of die attach areas;

forming an electrical interconnect extending from each of the semiconductor die to an associated one of the mold locks;

encapsulating all of the semiconductor die and the electrical interconnects in a unitary molded resin housing;

selectively etching through the sheet from the second side using the third etch resistant conductive material as an etch mask to form a plurality of isolated device lead contacts and a plurality of isolated device die contacts; and

sawing through the unitary molded resin housing to separate the plurality of semiconductor die into a plurality of individual device structures.

18. The process of claim 17 wherein the step of providing a sheet of conductive material comprises the step of providing a sheet of copper having a size and shape independent of the type of semiconductor die attached thereto.

19. The process of claim 17 wherein the step of providing the sheet of conductive material comprises the step of providing a layer of molybdenum sandwiched between two layers of copper.

20. The process of claim 17 wherein the step of selectively plating the first side of the sheet with a fourth conductive material to form a plurality of mold locks further comprises forming at least one of the mold locks in contact with a die attach area.

21. The process of claim 20 further comprising the step of attaching an electrical interconnection between the semiconductor die attached to a die attach area and the mold lock in contact with that die attach area.

22. The process of claim 17 wherein the step of attaching a semiconductor die comprises attaching at least two semiconductor die to each of the plurality of die attach areas.

23. The process of claim 17 wherein the step of encapsulating comprises the steps of:

placing the sheet of a first conductive material having semiconductor die attached thereto in a mold cavity, the mold cavity being independent of the type of semiconductor die attached to the sheet; and

filling the mold cavity with a resin material to form the unitary molded resin housing overlying the first side of the sheet of the first conductive material.

24. The process of claim 17 further comprising the step of electrically testing each of the semiconductor die after the step of selectively etching but before the step of sawing.

25. A process for manufacturing a plurality of semiconductor devices comprising the steps of:

providing a conductive sheet of material;

defining a plurality of die attach areas and a plurality of interconnect bond areas on a first surface of the conductive sheet;

attaching a plurality of semiconductor device die to the die attach areas;

providing an interconnection between each of the semiconductor device die and an associated one of the interconnect bond areas;

encapsulating the plurality of semiconductor device die in a unitary resin housing;

selectively etching the conductive sheet to remove first portions of the conductive sheet, leaving second portions of the conductive sheet coupled to the die attach areas and the interconnect bond areas; and

sawing through the unitary resin housing to singulate the semiconductor device die.

26. The process of claim 25 wherein the step of defining a plurality of interconnect bond areas comprises the steps of:

forming a plating mask layer having a plurality of openings therethrough on the first surface of the conductive sheet, the plurality of openings exposing regions of the first surface of the conductive sheet; and

plating the exposed regions with copper to form a plurality of mold locks extending above the surface of the conductive sheet, each of the mold locks having an upper surface forming an interconnect bond area.

27. The process of claim 25 wherein the step of selectively etching comprises the steps of:

applying a patterned etch mask to a second surface of the conductive sheet, the patterned etch mask comprising a plurality of masks in alignment with the plurality of die attach areas and the plurality of interconnect bond areas; and

etching portions of the second surface of the conductive sheet that are not covered by the plurality of masks.

28. A process for manufacturing a plurality of semiconductor devices comprising the steps of:

providing a sheet comprising copper, the sheet having first and second surfaces;

selectively plating the first surface of the sheet to form a plurality of die attach areas;

selectively plating the second surface of the sheet with a conductive etch resistant material to define a plurality of die contact areas and a plurality of bond contact areas, the die contact areas in alignment with the die attach areas;

selectively plating the first surface of the sheet with copper to form a plurality of mold locks, each of the mold locks aligned to respective ones of the plurality of bond contact areas and each of the mold locks having a bonding surface;

attaching a semiconductor die to each of the plurality of die attach areas;

providing an electrical interconnection between each of the semiconductor die and an associated one of the bonding surfaces;

forming a unitary resin housing encapsulating all of the semiconductor die;

etching the second surface of the sheet using the etch resistant conductive material as an etch mask to separate the sheet into a plurality of electrically isolated die contact areas and a plurality of bond contact areas; and

sawing through the unitary resin housing to singulate the semiconductor die into a plurality of semiconductor devices.

29. The process of claim 28 further comprising the step of electrically testing the semiconductor die after the step of etching the second surface and before the step of sawing.

30. The process of claim 28 wherein the step of selectively plating the second surface comprises selectively plating the second surface with sequential layers of nickel and palladium.