Transistor with an ultra short channel length defined by a laterally diffused nitrogen implant

• US 6,451,657 B1
• Filed: 02/08/2001
• Issued: 09/17/2002
• Est. Priority Date: 10/23/1998
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gardner, Mark I., May, Charles E., Fulford, H. Jim Jr.
• Primary Examiner(s): Pham, Long
• Application Number:
  US09/781,044
• Time in Patent Office: 586 Days
• Field of Search: 438/197, 438/528, 438/585, 438/299
• US Class Current: 438/299
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region. Portions of the gate conductor layer not covered by the oxide mask are then removed, leaving the reduced-width nitrogen free region as a gate conductor having a width below the photolithography threshold.

Claims

1. A method for making a transistor comprising defining an ultra-short channel length in an active region of a semiconductor substrate by implanting nitrogen into select regions of a gate conductor layer formed over said active region and laterally diffusing the nitrogen within the gate conductor to form the ultra-short channel length in a region of the gate conductor absent the nitrogen.

2. The method of claim 1, wherein laterally diffusing said nitrogen implant comprises annealing.

3. The method of claim 2, further comprising performing a thermal oxidation after said annealing.

4. The method of claim 2, wherein said anneal is carried out in the presence of an oxygen containing ambient.

5. The method of claim 2, wherein said gate conductor layer comprises polysilicon.

6. The method of claim 1, wherein the step of implanting nitrogen is performed with a nitrogen dose of approximately 1×

10¹³ to 1×

10¹⁹ atoms/cm³.

7. The method of claim 1, wherein said ultra-short channel length is smaller than the minimum resolvable dimensions achievable using photolithography.

8. A method for making a transistor, comprising:

providing a semiconductor substrate with a superjacent gate oxide layer;

depositing a gate conductor layer upon said gate oxide layer, wherein said gate conductor layer has an upper surface comprising a spaced pair of target regions;

implanting nitrogen into said spaced pair of target regions to form a spaced pair of nitrogen bearing regions, wherein the lateral distance between said spaced pair of nitrogen bearing regions defines a first width of a nitrogen free region;

heating said spaced pair of nitrogen bearing regions to form a spaced pair of diffused nitrogen regions, wherein the lateral distance between said spaced pair of diffused nitrogen regions defines a second width of said nitrogen free region less than said first width; and

removing said spaced pair of diffused nitrogen regions and underlying portions of said gate layer to form a Date conductor having a channel length equal to said second width.

9. The method of claim 8, wherein said first width is equal to or less than a minimum resolvable dimension achievable using photolithography.

10. The method of claim 8, further comprising determining said second width and calculating the temperature and duration of said heating step required to produce said second width.

11. The method of claim 8, wherein said gate conductor layer comprises polysilicon.

12. The method of claim 8, wherein the step of implanting nitrogen is performed with a nitrogen dose of approximately 1×

10¹³ to 1×

10¹⁹ atoms/cm³.

13. The method of claim 8, wherein said heating step comprises:

annealing said semiconductor substrate, including said spaced pair of nitrogen bearing regions, to form a spaced pair of diffused nitrogen regions, wherein the lateral distance between said spaced pair of diffused nitrogen regions defines a second width of said nitrogen free region less than said first width; and

thermally oxidizing said upper surface of said gate conductor layer to grow a variable thickness oxide layer over said upper surface of said gate conductor layer having a first oxide thickness grown over said spaced pair of diffused nitrogen regions and a second oxide thickness grown over said nitrogen free region.

14. The method of claim 13, wherein said annealing step is a rapid thermal anneal carried out at a temperature of approximately 900 to 1100°

C. for a duration of less than approximately 5 minutes.

15. The method of claim 13, wherein the step of thermally oxidizing said upper surface of said gate conductor is performed at a temperature of approximately 600-1150°

C.

16. The method of claim 13, wherein the step of thermally oxidizing said upper surface of said gate conductor is accomplished in an O₂ (dry) ambient.

17. The method of claim 13, wherein the step of thermally oxidizing said upper surface of said gate conductor is accomplished in an H₂O (wet) ambient.

18. The method of claim 8, wherein said heating step comprises annealing said semiconductor substrate in the presence of an oxygen containing ambient, thereby simultaneously forming said nitrogen free region with said second width and growing a variable thickness oxide layer over the gate conductor layer.

19. The method of claim 18, wherein said oxygen containing ambient is O₂.

20. The method of claim 18, wherein said oxygen containing ambient is H₂O.

21. The method of claims 13 or 18, wherein said removal step comprises:

anisotropically etching said variable thickness oxide layer to expose said pair of diffused nitrogen regions, thereby leaving a remaining oxide layer only over said nitrogen free region; and

using said remaining oxide layer as a mask, etching away exposed portions of said said gate conductor layer to leave a gate conductor having a channel length equal to said second width.