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Method for forming PLDD structure with minimized lateral dopant diffusion

  • US 6,451,704 B1
  • Filed: 05/07/2001
  • Issued: 09/17/2002
  • Est. Priority Date: 05/07/2001
  • Status: Expired due to Term
First Claim
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1. A method of creating Lightly doped Diffusion regions self-aligned with a PMOS device, comprising the steps of:

  • providing a silicon substrate, said substrate having been provided with at least one NMOS gate electrode and at least one PMOS gate electrode on the surface thereof, said at least one NMOS and at least one PMOS device being separated by a region of gate isolation created in the surface of said substrate, a Negative Lightly Doped Diffusion (NLDD) implantation self-aligned with said at least one NMOS gate electrode having been performed into the surface of said substrate, successive layers of oxide liner, etch stop material and first layer of top oxide having been deposited over the surface of the substrate including the surface of said gate electrodes;

    etching said first layer of top oxide, creating first gate spacers on sidewalls of said gate electrodes, using said layer of etch stop material as an etch stop;

    performing n-type Source/Drain (NS/D) and p-type Source/Drain (PS/D) implantations, said implantations being self-aligned with said at least one NMOS devices and said PMOS device respectively;

    removing said first gate spacers from sidewalls of said at least one NMOS gate electrode and said at least one PMOS gate electrode, exposing the surface of said layer of etch stop material;

    performing a Positive Lightly Doped Diffusion (PLDD) implantation, said PLDD implantation being self-aligned with said at least one PMOS devices, said PLDD implantation using boron as a source of ion impurities;

    depositing a second layer of top oxide over the surface of the substrate, including the surface of said at least one PMOS gate electrode and said at least one PMOS gate electrode;

    etching said second layer of top oxide, creating second gate spacers on sidewalls of said gate electrodes, using said layer of oxide liner as an etch stop layer; and

    etching said layer of etch stop material, using said layer of oxide liner as an etch stop layer.

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