High voltage mosgated device with trenches to reduce on-resistance

• US 6,452,230 B1
• Filed: 12/23/1999
• Issued: 09/17/2002
• Est. Priority Date: 12/23/1998
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Boden, Milton J. Jr.
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US09/471,343
• Time in Patent Office: 999 Days
• Field of Search: 257/192, 257/194, 257/195, 257/208, 257/296-297, 257/301, 257/302, 257/305, 257/408, 257/501, 257/502, 257/504, 257/506, 257/508, 257/510, 257/520, 257/326-329, 257/336, 257/341-344
• US Class Current: 257/341
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

Parallel, spaced SIPOS (semi-insulating polysilicon) filled trenches extend vertically through the epi layer of a MOSgated device and act to deplete carriers from the vertical conduction volume of the epi between trenches during voltage blocking conditions. Thus, a higher conductivity epi can be used to reduce the R_DSON (Drain to Source ON resistance) of the device for a given break down voltage.

Claims

1. A high voltage MOSgated device of low on-resistance comprising, in combination;

a thin flat chip of silicon having a main body layer of one conductivity type and having relatively high concentration and a junction-receiving layer of said one conductivity type and of a relatively lower concentration disposed atop said main body layer;

a plurality of spaced base diffusions of the other conductivity type formed in the upper surface of said junction receiving layer and a plurality of source regions of said one conductivity type formed in respective ones of said base diffusions to define invertable channel regions laterally spaced from one another by a vertical conduction channel region in said junction receiving layer; and

a MOSgate structure disposed above each of said invertible channels and responsive to a suitable MOSgate input signal;

a plurality of spaced thin trenches extending vertically from the top of said junction receiving layer for at least a major portion of the thickness of said junction receiving layer;

a first main contact disposed above the top surface of said junction receiving layer and in contact with said source and base diffusions and said trenches;

a second main contact formed on the bottom of said main body layer;

said trenches defining between them vertical depletable vertical conduction regions in said junction receiving layer for the length of said trenches;

each of said trenches being filled with a semi-insulating, non-injecting material which is relatively incapable of carrier injection into the junction receiving layer.

2. The device of claim, 1 wherein said semi-insulating material comprises a SIPOS semi-insulating polysilicon.

3. The device of claim 1, wherein said trenches are lined with silicon dioxide and are filled with polysilicon.

4. The device of claim 1, wherein said trenches have a depth which reaches said body layer.

5. The device of claim 2, wherein said trenches have a depth which reaches said body layer.

6. The device of claim 3, wherein said trenches have a depth which reaches said body layer.

7. The device of claim 1 wherein said trenches have a width of about 1 micron.