How to improve the ESD on SOI devices

• US 6,452,234 B1
• Filed: 11/27/2000
• Issued: 09/17/2002
• Est. Priority Date: 11/27/2000
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Mahanpour, Mehrdad
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Menz, Douglas
• Application Number:
  US09/722,222
• Time in Patent Office: 659 Days
• Field of Search: 257/357, 257/349, 257/350, 257/351
• US Class Current: 257/349
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A protection circuit structure for use with silicon-on-insulator integrated circuits is provided so as to improve electrostatic discharge protection capability. The protection circuit structure includes a P/N junction defining a protection diode. The protection diode is formed underneath an electrically conductive input pad associated with a conventional SOI semiconductor device.

Claims

1. A protection circuit structure for providing electrostatic discharge protection capability to silicon-on-insulator integrated circuits, said protection circuit structure comprising in combination:

a SOI structure including a transistor device including a source region, a drain region and a channel region all formed in a thin oxide layer overlying an insulating layer;

said insulating layer being formed over a p-type silicon substrate;

said thin oxide layer being formed over said insulating layer;

a p-type conductive region being formed in an upper portion of said insulating layer;

said p-type conductive region being spaced laterally apart from said SOI structure so that portions of said insulating layer surround the outer sides of said p-type conductive region to provide electrical isolation;

a metal conductive region being formed in the center of said p-type conductive region and extending between the top surface of said thin oxide layer and the bottom surface of said insulating layer;

an n-type conductive region being formed in said p-type silicon substrate adjacent to the bottom surface of said metal conductive region so as to define a protection diode with said p-type silicon substrate;

an electrically conductive input or input/output (I/O) pad formed over the top surface of said thin oxide layer; and

a conductive lead being operatively joined between said input pad and one of said source and drain regions of the transistor device.

2. A protection circuit structure as claimed in claim 1, further comprising a VSS power supply terminal connected to said silicon substrate.

3. A protection circuit structure as claimed in claim 2, wherein when an ESD event applies a high negative voltage to the input pad relative to the VSS power supply terminal, an electrically conductive path is formed through the protection diode which is forward biased.

4. A protection circuit structure as claimed in claim 2, wherein when an ESD event applies a high positive voltage to the input pad relative to the VSS power supply terminal, current will flow through the protection diode which is operated in a reverse breakdown mode.

5. A protection circuit structure as claimed in claim 2, wherein said silicon substrate serves as a heat sink so as to dissipate thermal energy created during an ESD event and normal operation.

6. A protection circuit structure as claimed in claim 1, wherein said insulating layer is formed of silicon dioxide.