Semiconductor device having a low dielectric layer as an interlayer insulating layer

• US 6,452,274 B1
• Filed: 11/16/1998
• Issued: 09/17/2002
• Est. Priority Date: 11/17/1997
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Nakayama, Hajime, Hasegawa, Toshiaki
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/192,335
• Time in Patent Office: 1,401 Days
• Field of Search: 257/643, 257/642, 257/759, 257/758, 257/700, 257/701, 257/750, 257/774, 257/748, 257/3
• US Class Current: 257/758
• CPC Class Codes: H01L 21/02115 the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
• CPC Class Codes: H01L 21/0212 the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/3127 Layers comprising fluoro (hydro)carbon compounds, e.g. polytetrafluoroethylene
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED

Abstract

A semiconductor device including a semiconductor substrate, an insulating layer formed on the substrate, a dielectric organic layer formed on the insulating layer and having a dielectric constant of not more than 3.0, and an interconnection layer in contact with the insulating layer in the dielectric organic layer, wherein the upper surface of the interconnection layer is formed higher than the upper surface of the dielectric organic layer, and a method of manufacture thereof.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

an insulating layer formed on the substrate;

a first dielectric layer formed on the insulating layer and having a dielectric constant of not more than 3.0; and

an interconnection layer formed in the first dielectric layer and contacting the insulating layer and extending with a substantially uniform composition to an upper surface that is formed higher than an upper surface of the first dielectric layer.

2. A semiconductor device as set forth in claim 1, further comprising a second dielectric layer formed on the interconnection layer and the first dielectric layer and having a dielectric constant of at least 3.0.

3. A semiconductor device as set forth in claim 1, wherein the first dielectric layer comprises at least one material selected from the group comprising a cyclic fluororesin, polytetrafluoroethylene, fluorinated ethylene propylene, a copolymer of tetrafluoroethylene and perfluoroalkoxyethylene, polyfluorovinylidene, polytrifluorochloroethylene, a fluoroaryl ether resin, polyfluoroimide, benzocyclobutene (BCB) polymer, polyimide, amorphous carbon, a monomethyltrihydroxysilane (organic SOG) condensate, a polymer having a repeating structural unit in its molecule of:

where, m and n represents a natural number,

a polymer having a repeating structural unit in its molecule of

where, x, y and z each represents a natural number,

a polymer having a repeating structural unit in its molecule of

where, R represents an alkylene or a phenylene group,

and a polymer having a repeating structural unit in its molecule of

where, R′

represents an alkylene or a phenylene group.

4. A semiconductor device as set forth in claim 2, wherein the second dielectric layer comprises at least one material selected from the group comprising a cyclic fluororesin, polytetrafluoroethylene, fluorinated ethylene propylene, a copolymer of tetrafluoroethylene and perfluoroalkoxyethylene, polyfluorovinylidene, polytrifluorochloroethylene, a fluoroaryl ether resin, polyfluoroimide, benzocyclobutene (BCB) polymer, polyimide, amorphous carbon, a monomethyltrihydroxysilane (organic SOG) condensate, a polymer having a repeating structural unit in its molecule of:

where, m and n each represents a natural number,

a polymer having a repeating structural unit in its molecule of

where, x, y and z each represents a natural number,

a polymer having a repeating structural unit in its molecule of

where, R represents an alkylene or a phenylene group,

and a polymer having a repeating structural unit in its molecule of

where, R′

represents an alkylene or a phenylene group.

5. A semiconductor device as set forth in claim 1, further comprising a dummy interconnection in the first dielectric layer in a portion of an interconnection space of at least three times a pitch in an interconnection pattern.

6. A semiconductor device as set forth in claim 5, wherein the dummy interconnection is formed in the portion of an interconnection space of at least three times the pitch so that all the interconnection spaces becomes less than 1 μ

m.

7. A semiconductor device as set forth in claim 5, further comprising a dummy contact hole formed in the insulating layer under the dummy interconnection and not connected with a lower conductive layer.

8. A semiconductor device comprising:

a semiconductor substrate;

an insulating layer formed on the substrate;

a layer containing xerogel on the insulating layer; and

an interconnection layer formed in the layer containing xerogel and contacting the insulating layer and extending with a substantially uniform composition higher than an upper surface of the layer containing xerogel.

9. A semiconductor device as set forth in claim 8, further comprising a dummy interconnection in the layer containing xerogel in a portion of an interconnection space of at least three times a pitch in an interconnection pattern.

10. A semiconductor device as set forth in claim 9, wherein the dummy interconnection is formed in the portion of an interconnection space of at least three times the pitch so that all the interconnection spaces becomes less than 1 μ

m.

11. A semiconductor device as set forth in claim 9, further comprising a dummy contact hole formed in the insulating layer under the dummy interconnection and not connected with a lower conductive layer.

12. A semiconductor device as set forth in claim 8, further comprising a layer containing a silane coupling agent in contact with the layer containing xerogel.

13. A semiconductor device as set forth in claim 8, wherein the layer containing xerogel is formed on the insulating layer at a portion of an interconnection space of at least three times a pitch in an interconnection pattern.

14. A semiconductor device comprising:

a semiconductor substrate;

an insulating layer formed on the substrate;

a first non-xerogel dielectric layer formed on the insulating layer and having a dielectric constant of not more than 3.0;

a layer containing xerogel on the first dielectric layer;

a second non-xerogel dielectric layer formed on the layer containing xerogel and having a dielectric constant of not more than 3.0; and

an interconnection layer formed in the layer containing xerogel and contacting the insulating layer.

15. A semiconductor device as set forth in claim 14, wherein an upper surface of the interconnection layer is formed higher than an upper surface of the layer containing xerogel.

16. A semiconductor device as set forth in claim 14, further comprising a contact hole formed in the second dielectric layer having a dielectric constant of not more than 3.0 for connecting interconnections.

17. A semiconductor device as set forth in claim 14, further comprising a dummy interconnection in the layer containing xerogel in a portion of an interconnection space of at least three times a pitch in an interconnection pattern.

18. A semiconductor device as set forth in claim 17, wherein the dummy interconnection is formed in the portion of an interconnection space of at least three times the pitch so that all the interconnection spaces becomes less than 1 μ

m.

19. A semiconductor device as set forth in claim 14, further comprising a dummy contact hole formed in the insulating layer under the dummy interconnection and not connected with a lower conductive layer.

20. A semiconductor device as set forth in claim 14, further comprising a layer containing a silane coupling agent in contact with the layer containing xerogel.