Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses
First Claim
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1. A test system comprising:
- a tester;
a reference device;
a communication channel communicatively interconnecting said tester and said reference device;
interface circuitry communicatively coupled to said channel and a plurality of semiconductor devices;
a state machine communicatively coupled to said interface circuitry, said state machine comprising;
a monitor state in which said interface circuitry monitors said communication channel, a write state, said state machine entering said write state upon detecting a write operation by said tester of test data to said reference device on said communication channel, said interface circuitry writing said test data detected on said communication channel to each of said semiconductor devices while said state machine is in said write state, and a read state, said state machine entering said read state upon detecting a read operation by said tester of response data from said reference device, said interface circuitry reading said response data detected on said communication channel and reading corresponding response data from each of said plurality of semiconductor devices while said state machine is in said read state; and
a comparator configured to compare said response data read from said reference device with said response data read from each of said semiconductor devices.
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Abstract
A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.
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Citations
26 Claims
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1. A test system comprising:
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a tester;
a reference device;
a communication channel communicatively interconnecting said tester and said reference device;
interface circuitry communicatively coupled to said channel and a plurality of semiconductor devices;
a state machine communicatively coupled to said interface circuitry, said state machine comprising;
a monitor state in which said interface circuitry monitors said communication channel, a write state, said state machine entering said write state upon detecting a write operation by said tester of test data to said reference device on said communication channel, said interface circuitry writing said test data detected on said communication channel to each of said semiconductor devices while said state machine is in said write state, and a read state, said state machine entering said read state upon detecting a read operation by said tester of response data from said reference device, said interface circuitry reading said response data detected on said communication channel and reading corresponding response data from each of said plurality of semiconductor devices while said state machine is in said read state; and
a comparator configured to compare said response data read from said reference device with said response data read from each of said semiconductor devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A test system comprising:
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a reference device;
test means for writing test data to said reference device and reading response data from said reference device;
interface means for communicating with a plurality of semiconductor devices;
channel means for providing at least one communication channel, said tester means, said reference device, and said interface means being communicatively interconnected to said channel means; and
state machine means for controlling said interface means, said state machine means comprising a monitor state, a write state, and a read state, wherein while in said monitor state, said state machine means causes said interface means to monitor said channel means, said state machine means enters said write state upon detecting a write operation by said test means of test data to said reference device on said channel means, and while in said write state, said state machine means causes said interface means to write said test data detected on said channel means to said semiconductor device, and said state machine means enters said read state upon detecting a read operation by said tester of response data from said reference device, and while in said read state, said state machine causes said interface means to read said response data detected on said channel means and to read corresponding response data from said semiconductor device. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification