Efficient parallel testing of integrated circuit devices using a known good device to generate expected responses

• US 6,452,411 B1
• Filed: 03/01/1999
• Issued: 09/17/2002
• Est. Priority Date: 03/01/1999
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Roy, Richard S.
• Primary Examiner(s): Sherry, Michael
• Assistant Examiner(s): KOBERT, RUSSELL MARC
• Application Number:
  US09/260,460
• Time in Patent Office: 1,296 Days
• Field of Search: 324/754, 324/765, 324/158.1, 714/736, 714/735, 714/737
• US Class Current: 324/754.07
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924

Abstract

A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the tester is reading from the locations in the known good device (KGD), and in response performs a comparison between DUT data read from the corresponding locations in the DUTs and expected responses obtained form the KGD.

Claims

1. A test system comprising:

a tester;

a reference device;

a communication channel communicatively interconnecting said tester and said reference device;

interface circuitry communicatively coupled to said channel and a plurality of semiconductor devices;

a state machine communicatively coupled to said interface circuitry, said state machine comprising;

a monitor state in which said interface circuitry monitors said communication channel,

a write state, said state machine entering said write state upon detecting a write operation by said tester of test data to said reference device on said communication channel, said interface circuitry writing said test data detected on said communication channel to each of said semiconductor devices while said state machine is in said write state, and

a read state, said state machine entering said read state upon detecting a read operation by said tester of response data from said reference device, said interface circuitry reading said response data detected on said communication channel and reading corresponding response data from each of said plurality of semiconductor devices while said state machine is in said read state; and

a comparator configured to compare said response data read from said reference device with said response data read from each of said semiconductor devices.

2. The system of claim 1, wherein results of said comparison by said comparator are communicated to said tester over said communication channel.

3. The system of claim 1 further comprising a second communication channel, wherein results of said comparison by said comparator are communicated to said tester over said second channel.

4. The system of claim 1 further comprising a memory for storing results of said comparison by said comparator.

5. The system of claim 1 further comprising means for comparing semiconductor device timing with reference device timing, said reference device timing being obtained by monitoring said channel while said tester is writing to and reading from said reference device.

6. The system of claim 1 further comprising a probe card, said probe card comprising a plurality of probes for contacting signal points on said semiconductor devices, each said probe communicatively coupled to said interface circuitry.

7. The system of claim 6, wherein said interface circuitry is disposed on said probe card.

8. The system of claim 6, wherein said reference device is disposed on said probe card.

9. The system of claim 6, wherein said state machine is disposed on said probe card.

10. The system of claim 6, wherein said comparator is disposed on said probe card.

11. The system of claim 6, wherein at least two of said interface circuitry, said reference device, said state machine, and said comparator are disposed on said probe card.

12. The system of claim 6, wherein at least three of said interface circuitry, said reference device, said state machine, and said comparator are disposed on said probe card.

13. The system of claim 6, wherein said interface circuitry, said reference device, said state machine, and said comparator are disposed on said probe card.

14. A test system comprising:

a reference device;

test means for writing test data to said reference device and reading response data from said reference device;

interface means for communicating with a plurality of semiconductor devices;

channel means for providing at least one communication channel, said tester means, said reference device, and said interface means being communicatively interconnected to said channel means; and

state machine means for controlling said interface means, said state machine means comprising a monitor state, a write state, and a read state, wherein

while in said monitor state, said state machine means causes said interface means to monitor said channel means,

said state machine means enters said write state upon detecting a write operation by said test means of test data to said reference device on said channel means, and while in said write state, said state machine means causes said interface means to write said test data detected on said channel means to said semiconductor device, and

said state machine means enters said read state upon detecting a read operation by said tester of response data from said reference device, and while in said read state, said state machine causes said interface means to read said response data detected on said channel means and to read corresponding response data from said semiconductor device.

15. The system of claim 14 further comprising comparator means for comparing said response data read from said reference device with said response data read from each of said semiconductor devices.

16. The system of claim 15 further comprising means for communicating a result of said comparison by said comparison means to said test means.

17. The system of claim 16 further comprising memory means for storing a result of said comparison by said comparison means.

18. The system of claim 16 further comprising means for comparing timing associated with said semiconductor devices with timing associated with said reference device, said timing associated with said reference device being obtained by monitoring said channel means while said test means is writing to and reading from said reference device.

19. The system of claim 14 further comprising probing means for contacting signal points on said semiconductor devices.

20. The system of claim 19, wherein said interface means is disposed on said probing means.

21. The system of claim 19, wherein said reference device is disposed on said probing means.

22. The system of claim 19, wherein said state machine means is disposed on said probing means.

23. The system of claim 19, wherein said comparator means is disposed on said probing means.

24. The system of claim 19, wherein at least two of said interface means, said reference device, said state machine, and said comparator means are disposed on said probing means.

25. The system of claim 19, wherein at least three of said interface means, said reference device, said state machine, and said comparator means are disposed on said probing means.

26. The system of claim 19, wherein said interface means, said reference device, said state machine, and said comparator means are disposed on said probing means.