Pixel buffer circuits for implementing improved methods of displaying grey-scale or color images

• US 6,452,589 B1
• Filed: 07/21/1998
• Issued: 09/17/2002
• Est. Priority Date: 07/20/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: The Board of Regents of the University of Colorado (University of Colorado System)
• Inventors: McKnight, Douglas J.
• Primary Examiner(s): Chang, Kent
• Application Number:
  US09/119,976
• Time in Patent Office: 1,519 Days
• Field of Search: 345/87, 345/89, 345/90, 345/98, 345/99, 345/55, 345/205, 345/213, 345/148, 345/186, 345/508, 345/518, 345/147
• US Class Current: 345/205
• CPC Class Codes: G06T 3/40 Scaling of whole images or parts thereof, e.g. expanding or contracting
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0823 used to establish symmetry in driving, e.g. with polarity inversion
• CPC Class Codes: G09G 2300/0828 forming a digital to analog [D/A] conversion circuit
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0847 being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2320/0266 Reduction of sub-frame artefacts
• CPC Class Codes: G09G 2320/0633 by amplitude modulation of the brightness of the illumination source
• CPC Class Codes: G09G 2320/064 by time modulation of the brightness of the illumination source
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2033 : with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• CPC Class Codes: G09G 3/2037 : with specific control of sub-frames corresponding to the least significant bits
• CPC Class Codes: G09G 3/3406 : Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336
• CPC Class Codes: G09G 3/3648 : using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 : the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

A device such as a display device or a spatial light modulator can store pixel data in a plurality of small circuits coupled to pixel mirrors and simultaneously drive these pixel mirrors a frame at a time. This device is particularly beneficial for implementing improved image quality techniques which can convert binary images to grey-scale images and/or separate red, green and blue images into color images and displaying those images using the natural process of integration which occurs when a person views images at sufficiently high rates.

Claims

1. A display device comprising:

a substrate;

a pixel array arranged on said substrate comprising a plurality of pixels, wherein each of said pixels comprises;

a pixel electrode;

a driving circuit coupled to said pixel electrode for switching a data signal to said pixel electrode at a present pixel value; and

at least three storage devices contained within said driving circuit, wherein each of said at least three storage devices stores future pixel values corresponding to one of three colors while said pixel electrode is at said present pixel value; and

a processor coupled to said pixel array, said processor controlling the transfer of said future pixel values from said at least three storage devices to said pixel electrode.

2. The device of claim 1, wherein the three colors comprise red, green and blue.

3. The device of claim 1, wherein the pixel array comprises a reflective pixel array.

4. A liquid crystal on silicon display comprising the display device of claim 3.

5. The device of claim 1, wherein each driving circuit comprises:

a first transistor having a first electrode connected to selectively receive a first prescribed voltage, a control electrode connected to receive the pixel values and a second electrode connected to the pixel electrode at a connection point; and

a reset circuit connected to the connection point.

6. The device of claim 1, wherein each driving circuit comprises:

a first transistor having a first electrode connected to selectively receive a first prescribed voltage and a second electrode connected to the pixel electrode at a connection point;

a second transistor having a first electrode connected to selectively receive the first prescribed voltage and a second electrode connected to the connection point;

a third transistor having a first electrode connected to selectively receive the first prescribed voltage and a second electrode connected to the connection point; and

a reset circuit connected to the connection point.

7. The device of claim 6, wherein the at least three storage devices comprise first, second and third storage devices that include the first, second and third transistors, respectively.

8. A device, comprising:

a substrate;

a pixel array arranged on said substrate comprising a plurality of pixels, wherein each of said pixels comprises;

a pixel electrode;

a driving circuit coupled to said pixel electrode for driving said pixel electrode at a present pixel value, wherein the driving circuit includes a driving unit consisting of a single element, and

a holding unit contained within said driving unit for holding a future pixel value while said pixel electrode is at said present pixel value; and

a processor coupled to said pixel array, said processor controlling the transfer of said future pixel value from said holding unit to said pixel electrode.

9. The device of claim 8, wherein said single element is a transistor, and wherein the transistor is the driving unit and the holding unit.

10. The device of claim 8, wherein said driving circuit includes three driving units each consisting of a single element, wherein said holding unit is adapted to concurrently hold at least one of read, green and blue future pixel values.

11. A device, comprising:

a substrate;

a pixel array arranged on said substrate comprising a plurality of pixels, wherein each of said pixels comprises;

a driving circuit for driving said pixel at a present pixel value, wherein the driving circuit comprises,

a first transistor having a first electrode connected to a first prescribed voltage,

a second transistor having a first electrode connected to a second electrode of the first transistor; and

a third transistor having a first electrode connected at a connection point to a second electrode of the second transistor and the pixel, wherein a second electrode of the third transistor is connected to a second prescribed voltage; and

a holding unit contained within said driving circuit for receiving and holding at least one future pixel value while said pixel is at said present pixel value.

12. The device of claim 11, wherein a control electrode of the second transistor receives the pixel values through a selector controlled by a first control signal, and wherein the second transistor is the holding unit.

13. The device of claim 11, wherein the driving circuit further comprises:

a fourth transistor having a first electrode connected to the first prescribed voltage; and

a fifth transistor having a first electrode connected to a second electrode of the fourth transistor, and a second electrode connected to the connection point, and wherein a control electrode of the fifth transistor receives the pixel values through a selector controlled by a fourth control signal.

14. The device of claim 11, further comprising:

fourth and sixth transistors having a first electrode connected to the first prescribed voltage; and

fifth and seventh transistors, each having a first electrode respectively connected to a second electrode of the fourth and sixth transistors, wherein second electrodes of the fifth and seventh transistors are connected to the connection point, and wherein control electrodes of the second, fifth and seventh transistors receive the pixel values through a selector, and wherein the holding unit includes the second, fifth and seventh transistors, and wherein the holding unit is adapted to concurrently hold three future pixel values.