Integrated graphics processing unit with antialiasing

• US 6,452,595 B1
• Filed: 11/27/2000
• Issued: 09/17/2002
• Est. Priority Date: 12/06/1999
• Status: Expired due to Term

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Molnar, Steven E., Montrym, John S., Voorhies, Douglas A.
• Primary Examiner(s): Zimmerman, Mark
• Assistant Examiner(s): Stevenson, Philip H.
• Application Number:
  US09/724,206
• Time in Patent Office: 659 Days
• Field of Search: 345/426, 345/611, 345/419, 345/427, 345/519
• US Class Current: 345/426
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G06T 15/50 Lighting effects
• CPC Class Codes: G06T 15/503 Blending, e.g. for anti-aliasing
• CPC Class Codes: G06T 15/506 Illumination models

Abstract

A graphics pipeline system is provided for graphics processing. Such system includes a transform module adapted for receiving vertex data. The transform module serves to transform the vertex data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the vertex data received from the lighting module. During use, an antialiasing feature is implemented to improve a quality of the graphics rendering.

Claims

1. A graphics pipeline system for graphics processing, comprising:

a transform module adapted for receiving graphics data, the transform module being positioned on a single semiconductor platform for transforming the graphics data from a first space to a second space;

a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module for performing lighting operations on the graphics data;

a set-up module positioned on the same single semiconductor platform as the transform module and the lighting module for setting up the graphics data;

a render module positioned on the same single semiconductor platform as the transform module, the lighting module, and the set-up module for rendering the graphics data; and

memory positioned on the same single semiconductor platform as the transform module, the lighting module, the set-up module, and the render module for storing the graphics data;

wherein antialiasing is performed on the single semiconductor platform to improve a quality of the rendering;

wherein the single semiconductor platform operates with an application program interface.

2. The system as set forth in claim 1, wherein the rendering includes 3-D rendering.

3. The system as set forth in claim 1, wherein the single semiconductor platform operates with application program interface.

4. The system as set forth in claim 1, wherein a vertex fog operation is performed on the graphics data utilizing the single semiconductor platform.

5. The system as set forth in claim 1, wherein the transforming is performed utilizing an add operation and a multiply operation.

6. The system as set forth in claim 1, wherein the lighting operations are performed utilizing an add operation and a multiply operation.

7. The system as set forth in claim 1, wherein at least one mode bit is utilized to control the transforming at least in part.

8. The system as set forth in claim 1, wherein at least one mode bit is utilized to control the lighting operations at least in part.

9. The system as set forth in claim 1, wherein a fog operation is performed on the graphics data utilizing the single semiconductor platform.

10. The system as set forth in claim 1, wherein the single semiconductor platform includes a chip.

11. The system as set forth in claim 1, wherein texture mapping is performed on the single semiconductor platform.

12. The system as set forth in claim 1, wherein the antialiasing includes supersampling.

13. The system as set forth in claim 1, wherein the antialiasing includes multisampling.

14. The system as set forth in claim 1, wherein the antialiasing includes fragment-based antialiasing.

15. A method for graphics processing utilizing a single semiconductor platform, comprising:

transforming graphics data;

lighting the graphics data;

setting up the graphics data; and

rendering the graphics data;

wherein the graphics data is transformed, lighted, set up, and rendered on the single semiconductor platform;

wherein antialiasing is performed on the single semiconductor platform;

wherein the single semiconductor platform operates with an application program interface.

16. The method as set forth in claim 15, wherein the rendering includes 3-D rendering.

17. The method as set forth in claim 15, wherein the single semiconductor platform operates with application program interface.

18. The method as set forth in claim 15, wherein the transforming is performed utilizing an add operation and a multiply operation.

19. The method as set forth in claim 15, wherein the lighting is performed utilizing an add operation and a multiply operation.

20. The method as set forth in claim 15, wherein at least one mode bit is utilized to control the transforming at least in part.

21. The method as set forth in claim 15, wherein at least one mode bit is utilized to control the lighting at least in part.

22. The method as set forth in claim 15, wherein a fog operation is performed on the graphics data utilizing the single semiconductor platform.

23. The method as set forth in claim 15, wherein blending is performed on the graphics data utilizing the single semiconductor platform.

24. The method as set forth in claim 15, wherein the single semiconductor platform includes a chip.

25. The method as set forth in claim 15, wherein texture mapping is performed on the single semiconductor platform.

26. The method as set forth in claim 15, wherein the antialiasing includes supersampling.

27. The method as set forth in claim 15, wherein the antialiasing includes multisampling.

28. The method as set forth in claim 15, wherein the antialiasing includes fragment-based antialiasing.

29. A graphics pipeline system for graphics processing, comprising:

a transform module adapted for receiving graphics data, the transform module being positioned on a single semiconductor platform for transforming the graphics data from a first space to a second space;

a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module for performing lighting operations on the graphics data;

a set-up module positioned on the same single semiconductor platform as the transform module and the lighting module for setting up the graphics data;

a render module positioned on the same single semiconductor platform as the transform module, the lighting module, and the set-up module for rendering the graphics data; and

memory positioned on the same single semiconductor platform as the transform module, the lighting module, the set-up module, and the render module for storing the graphics data;

wherein antialiasing and texture mapping are performed on the single semiconductor platform;

wherein the single semiconductor platform operates with an application program interface.

30. A method for graphics processing utilizing a single semiconductor platform, comprising:

transforming graphics data;

lighting the graphics data;

setting up the graphics data; and

rendering the graphics data;

wherein the graphics data is transformed, lighted, set up, and rendered on the single semiconductor platform;

wherein antialiasing and texture mapping are performed on the single semiconductor platform;

wherein the single semiconductor platform operates with an application program interface.

31. A method for graphics processing, comprising:

transforming graphics data from a first space to a second space;

lighting the graphics data;

setting up the graphics data;

performing a clipping operation on the graphics data; and

3-D rendering the graphics data;

wherein the graphics data is set up, transformed, lighted, and rendered, and the clipping operation is performed, on a single semiconductor platform;

wherein the single semiconductor platform operates with an application program interface; and

wherein antialiasing and texture mapping are performed on the single semiconductor platform;

wherein the single semiconductor platform is capable of being coupled to a central processing unit.

32. A graphics pipeline system for graphics processing, comprising:

a transform module adapted for receiving graphics data, the transform module being positioned on a single semiconductor platform for transforming the graphics data from a first space to a second space;

a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module for performing lighting operations on the graphics data;

a set-up module positioned on the same single semiconductor platform as the transform module and the lighting module for setting up the graphics data;

a render module positioned on the same single semiconductor platform as the transform module, the lighting module, and the set-up module for rendering the graphics data;

memory positioned on the same single semiconductor platform as the transform module, the lighting module, the set-up module, and the render module for storing the graphics data; and

means for antialiasing and texture mapping on the single semiconductor platform;

wherein the single semiconductor platform operates with an application program interface.

33. A single-platform graphics pipeline system, comprising:

a transform module positioned on a single semiconductor platform for transforming graphics data;

a lighting module positioned on the same single semiconductor platform as the transform module, the lighting module being for performing lighting operations on the graphics data;

a set-up module positioned on the same single semiconductor platform as the transform module and the lighting module, the set-up module being for setting up the graphics data; and

a rendering module positioned on the same single semiconductor platform as the transform module and the lighting module, the rendering module being for 3-D rendering of the graphics data;

wherein a clipping operation is performed utilizing the single semiconductor platform;

memory positioned on the same single semiconductor platform as the transform module, the lighting module, the set-up module, and the render module for storing the graphics data;

wherein the graphics data is blended utilizing the single semiconductor platform for blending triangles represented by vertex data associated with the graphics data;

wherein a vertex fog operation is performed on the graphics data utilizing the single semiconductor platform;

wherein antialiasing and texture mapping are performed on the single semiconductor platform;

wherein the single semiconductor platform operates with an application program interface;

wherein the single semiconductor platform is capable of being coupled to a central processing unit for receiving instructions therefrom.