Packaging architecture for 32 processor server

• US 6,452,789 B1
• Filed: 04/29/2000
• Issued: 09/17/2002
• Est. Priority Date: 04/29/2000
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Morris, Terrel L., Peterson, Eric C., Day, Michael C., Belady, Christian L, Pallotti, Lisa Heid
• Primary Examiner(s): Schuberg, Darren
• Assistant Examiner(s): DATSKOVSKIY, MICHAIL V
• Application Number:
  US09/562,593
• Time in Patent Office: 871 Days
• Field of Search: G06/F.116, G06/F.124, G06/F 1.516, 361/683, 361/684, 361/686, 361/685, 361/724, 361/727, 361/688, 361/695, 361/788, 361/800, 364/708.1, 364/245.7, 364/251.7, 364/259.9, 312/223.1, 312/223.2, 312/223.3, 363/141, 363/144, 363/147, 710/102, 211/26, 211/26.2, 211/41.17, 439/61, 439/59, 439/64, 439/65, 439/25, 439/74, 174/261, 174/158.R, 174/32, 395/401, 395/410, 395/412, 395/427, 395/474, 395/309, 395/310, 395/162-166, 701/13
• US Class Current: 361/679.02
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

The inventive system uses a backplane to interconnect a plurality of modular cell boards. Each cell board comprises a plurality of processors, a processor controller chip, a memory subsystem, and a power subsystem. The processor controller chip manages communications between components on the cell board. A mechanical subassembly provides support for the cell board, as well as ventilation passages for cooling. Controller chips are connected to one side of the backplane, while the cell boards are connected to the other side. The controller chips manage cell board to cell board communications, and communications between the backplane and the computer system. The cell boards are arranged in back to back pairs, with the outer most cell boards having their components extend beyond the height of the backplane. This allows for an increase of spacing between the front to front interface of adjacent cell boards.

Claims

1. A multi-processor computer system comprising:

a plurality of cell boards, wherein each cell board includes;

a plurality of processors;

a memory subsystem for storing data for the plurality of processors; and

a power subsystem for providing power to the plurality of processors and the memory subsystem; and

a backplane having;

a first side that connects with the plurality of cell boards; and

a second side that connects;

a plurality of power boards for providing power to said power subsystem;

a plurality of controller devices; and

a plurality of connectors for connecting wiring to remote I/O.

2. The multi-processor computer system of claim 1 wherein each cell board further includes:

a processor agent device that controls communication between the plurality of processors and the memory subsystem and between the plurality of processors and the backplane.

3. The multi-processor computer system of claim 1 wherein:

each cell board has a first side panel that includes a plurality of ventilation holes; and

each cell board has a second side panel that includes a plurality of ventilation holes;

wherein the first side panel and the second side panel allow cooling air to flow across the cell board.

4. The multi-processor computer system of claim 3 wherein:

the plurality of processors and the power subsystem include heat sinks having fins, and the memory subsystem includes a plurality of memory modules;

wherein the fins and the memory modules are arrangement to reduce turbulence in the flow of the cooling air.

5. The multi-processor computer system of claim 1 wherein:

each cell board of the plurality of cell boards may be replaced while the computer system is on-line;

wherein each cell board includes a handle to facilitate replacement.

6. The multi-processor computer system of claim 3 wherein:

each cell board of the plurality of cell board has a first side and a second side; and

wherein

the plurality of processors, the memory subsystem, and the power subsystem are connected to the first side.

7. The multi-processor computer system of claim 6 wherein:

a first cell board is connected to the backplane such that the first side is facing away from the interior of an area formed by the perimeter of the backplane;

wherein at least one of the plurality of processors, the memory subsystem, and the power subsystem has a height that exceeds the area of the backplane.

8. The multi-processor computer system of claim 7 wherein:

a second cell board is connected to the backplane such that its second side is adjacent to the second side of the first cell board;

a third cell board is connected to the backplane such that its first side is adjacent to the first side of the second cell board; and

a fourth cell board is connected to the backplane such that its second side is adjacent to the second side of the third cell board.

9. The multi-processor computer system of claim 7 wherein:

the plurality of power boards receive power from the computer system and provide power to each power subsystem of the plurality of cell boards; and

the plurality of controller devices that control communication between the plurality of processors and the backplane, and between the backplane and the computer system.

10. The multi-processor computer system of claim 9 wherein the backplane further includes:

at least one air passage that allows cooling air to pass over the plurality of power boards and the plurality of controller devices.

11. A cell board for a multi-processor computer system, wherein the cell board comprises:

a plurality of processors;

a memory subsystem for storing data for the plurality of processors;

a power subsystem for providing power to the plurality of processors and the memory subsystem; and

wherein the cell board is connected to a first side of a backplane in a computer system and wherein the backplane has a second side that connects;

a plurality of power boards for providing power to said power subsystem;

a plurality of controller devices; and

a plurality of connectors for connecting wiring to remote I/O.

12. The cell board of claim 11 further comprising:

a processor agent device that controls communication between the plurality of processors and the memory subsystem.

13. The cell board of claim 11 further comprising:

a first side panel that includes a plurality of ventilation holes; and

a second side panel that includes a plurality of ventilation holes;

wherein the first side panel and the second side panel allow cooling air to flow across the cell board.

14. The cell board of claim 13 wherein:

the plurality of processors and the power subsystem include heat sinks having fins, and the memory subsystem includes a plurality of memory modules;

wherein the fins and the memory modules are arrangement to reduce turbulence in the flow of the cooling air.

15. The cell board of claim 11 wherein the cell board may be replaced while the computer system is on-line, the cell board further comprises:

a handle to facilitate replacement.

16. The cell board of claim 13 wherein:

the cell board has a first side; and

the plurality of processors, the memory subsystem, and the power subsystem are connected to the first side.

17. The cell board of claim 11 wherein:

the cell board is one of a plurality of cell boards of the computer system.

18. A multi-processor computer system comprising:

a plurality of cell boards, wherein each cell board includes;

a plurality of processors;

a memory subsystem for storing data for the plurality of processors; and

a power subsystem for providing power to the plurality of processors and the memory subsystem; and

a backplane having;

a first side that connects with the plurality of cell boards,

a plurality of power boards for receiving power from the computer system and providing power to each power subsystem of the plurality of cell boards;

a plurality of controller devices that control communication between the plurality of processors and the backplane, and between the backplane and the computer system; and

a plurality of connectors for connecting wiring to remote I/O;

wherein the plurality of power boards, the plurality of controller devices, and the plurality of connectors are connected to a second side of the backplane;

wherein each cell board has a first side and a second side, with the plurality of processors, the memory subsystem, and the power subsystem are connected to the first side;

wherein a first cell board is connected to the backplane such that the first side is facing away from the interior of an area formed by the perimeter of the backplane, and at least one of the plurality of processors, the memory subsystem, and the power subsystem has a height that exceeds the area of the backplane; and

wherein each cell board has;

a first side panel that includes a plurality of ventilation holes; and

a second side panel that includes a plurality of ventilation holes;

wherein the first side panel and the second side panel allow cooling air to flow across the cell board.