Nonvolatile memory system, semiconductor memory and writing method

• US 6,452,838 B1
• Filed: 11/27/2001
• Issued: 09/17/2002
• Est. Priority Date: 07/09/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Inventors: Ishii, Tatsuya, Tsuchiya, Osamu, Miwa, Hitoshi, Kubono, Shooji
• Primary Examiner(s): Lebentritt, Michael S.
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/993,685
• Publication Number:
  US 20020054511A1
• Time in Patent Office: 294 Days
• Field of Search: 365/185.24, 365/185.19, 365/185.29, 365/185.22, 365/185.18
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Claims

1. A nonvolatile memory system comprising:

a plurality of nonvolatile memories; and

a controller,

wherein each of said plurality of nonvolatile memories has a plurality of nonvolatile memory cells and a plurality of word lines each of which coupled to ones of said plurality of said nonvolatile memory cells;

wherein each of said nonvolatile memory cells has a threshold voltage within one of a plurality of threshold voltage ranges,

wherein said controller supplies a first operation command and a second operation command to at least one nonvolatile memory,

wherein in an operation of said first operation command, said nonvolatile memory selects one of said word lines and supplies a first voltage to said selected word line during a first predetermined time, and

wherein in an operation of said second operation command, said nonvolatile memory selects ones of said word lines and supplies said first voltage to said selected word line during a second predetermined time.

2. A nonvolatile memory system according to claim 1,

wherein said first predetermined time is shorter than said second predetermined time.

3. A nonvolatile memory system according to claim 2,

each of said nonvolatile memory further comprises a data storing circuit for storing data,

wherein each of said threshold voltage ranges corresponds to data,

wherein after supplying first voltage in said operation of said first operation command, said nonvolatile memory supplies a second voltage to said selected word line in order to change threshold voltage of said nonvolatile memory cells within one of threshold voltage ranges corresponding to data stored in said data storing circuit.

4. A nonvolatile memory system comprising:

a plurality of nonvolatile memories; and

a controller,

wherein each of said nonvolatile memories has a plurality of threshold voltage ranges, a plurality of word lines each of which coupled to ones of said plurality of nonvolatile memories and a data storing circuit for storing data,

wherein said controller supplies a first operation command and a second operation command,

wherein in an operation of said first operation command, said nonvolatile memory selects one of said word lines, supplies a first level voltage to said selected word line during a first predetermined time and next supplies a second level voltage to said selected word line during a second predetermined time corresponding to data in said data storing circuit,

wherein in an operation of said second operation command, said nonvolatile memory selects one of said word lines, supplies said first level voltage to said selected word line during a third predetermined time longer than said first predetermined time and next supplies said second level voltage to said selected word line during said second predetermined time.

5. A nonvolatile memory system according to claim 4,

wherein said first level voltage is for changing threshold voltage of said nonvolatile memory cells toward an erase level, and said second level voltage is for changing threshold voltage toward a write level.

6. A nonvolatile memory system according to claim 5,

wherein said threshold voltage of said nonvolatile memory cells has been changed to an intermediate level toward said erase level, when said first level voltage is supplied during said first predetermined time, and

wherein said threshold voltage of said nonvolatile memory cells has been changed to said erase level, when said first level voltage is supplied during said third predetermined time.